54AC11112 Search Results

54AC11112 Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
54AC11112		Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET	Original	PDF	117.59KB	6
54AC11112		Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET	Original	PDF	94.17KB	7
54AC11112FK		Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET	Original	PDF	94.18KB	7
54AC11112FK		Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET	Scan	PDF	155.16KB	6
54AC11112J		Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET	Original	PDF	94.18KB	7
54AC11112J		Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET	Scan	PDF	155.16KB	6

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Texas Instruments 54AC11112FK Peripheral ICs
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	54AC11112FK		1,489			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments 54AC11112J Peripheral ICs
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Vyrian	54AC11112J		1,258			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Texas Instruments SNJ54AC11112J Peripheral ICs
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Vyrian	SNJ54AC11112J		1,213			1 - 10 - 100 - 1000 - 10000 -	Get Quote

54AC11112 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
54AC11112 Abstract: 74AC11112 Contextual Info: 54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0101— D3334, JU N E 1989— REVISED M AR CH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11112 . . . J PACKAGE 74AC11112 . . . D OH N PACKAGE TOP VIEW	OCR Scan	54AC11112, 74AC11112 TI0101â D3334, 500-mA 300-mil 54AC11112	PDF
54AC11112 Abstract: 74AC11112 Contextual Info: 54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • • • • • 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes	Original	54AC11112, 74AC11112 SCAS073A 54AC11112 500-mA STD-883C 300-mil 54AC11112 74AC11112	PDF
Contextual Info: 54AC11112,74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D3334, JUNE 1989 - REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configuration Minimizes High-Speed Switching Noise EPIC m Enhanced-Performance Implanted	OCR Scan	54AC11112 74AC11112 D3334, 500-mA STD-883C 300-mil 54AC11112. 74AC11112	PDF
Contextual Info: 54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • • • • • 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes	Original	54AC11112, 74AC11112 SCAS073A 54AC11112 500-mA STD-883C 300-mil	PDF
Contextual Info: 54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET T I0 101— 0 3 3 3 4 . JUNE 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE TOP VIEW	OCR Scan	54AC11112, 74AC11112 500-mA 300-mil	PDF
Contextual Info: 54AC11112, 74AC11112 DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET ăą SCAS073A − JUNE 1989 − REVISED APRIL 1993 • • • • • 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes	Original	54AC11112, 74AC11112 SCAS073A 54AC11112 500-mA STD-883C 300-mil	PDF
54AC11112 Abstract: 74AC11112 2j115 Contextual Info: 54AC11112, 74AC11112 DUAL JĆK NEGATIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET ăą SCAS073A − JUNE 1989 − REVISED APRIL 1993 • • • • • 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes	Original	54AC11112, 74AC11112 SCAS073A 54AC11112 500-mA STD-883C 300-mil 54AC11112 74AC11112 2j115	PDF
Contextual Info: 54AC11112,74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ Flow-Through Architecture Optimizes PCB Layout D3334, JUNE 1 9 8 9 - REVISED APRIL 1993 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE	OCR Scan	54AC11112 74AC11112 D3334, 500-mA STD-883C 300-mil 54AC11112 74AC11112 DM435fl	PDF
54AC11112 Abstract: 74AC11112 Contextual Info: 54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • • • • • 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes	Original	54AC11112, 74AC11112 SCAS073A 54AC11112 500-mA STD-883C 300-mil 54AC11112 74AC11112	PDF
Contextual Info: 54ACT11109,74ACT11109 DUALJ-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, FEBRUARY 1987 - REVISED APRIL 1993_ logic symbol* 1Q 1Q 2Q 2Q t This symbol is In accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.	OCR Scan	54ACT11109 74ACT11109 D2957, fl3bl723	PDF