54LS114A Search Results
54LS114A Datasheets (3)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| 54LS114A/BCAJC | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 36.57KB | 1 | ||
| 54LS114A/BDAJC | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 36.57KB | 1 | ||
| 54LS114AM/B2AJC | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 36.57KB | 1 |
54LS114A Price and Stock
Motorola Semiconductor Products 54LS114A/BCAJCIC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,DIP,14PIN,CERAMIC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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54LS114A/BCAJC | 9 |
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| 54LS114A/BCAJC | 8 |
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Buy Now | ||||||||
Texas Instruments SN54LS114AJ-00J-K Flip-Flop, LS Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN54LS114AJ-00 | 21,200 |
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Texas Instruments SN54LS114AWJ-K Flip-Flop, LS Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDFP14 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN54LS114AW | 14,850 |
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Texas Instruments SN54LS114AFKJ-K Flip-Flop, LS Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN54LS114AFK | 12,150 |
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Texas Instruments SN54LS114AW-10J-K Flip-Flop, LS Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDFP14 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN54LS114AW-10 | 11,600 |
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54LS114A Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: M M O T O R O L A Military 54LS114A D u a l J -K Flip-Flop W ith Preset, C o m m o n C le ar and C o m m o n C lo c k MIL-M-38510/30105 T h e 5 4 L S 1 1 4 A o ffe rs c o m m o n clock a n d c o m m o n clear inputs and in d ivid u al J, K, and set inputs. Th e se m o n o lith ic dual flip -flo p s are |
OCR Scan |
mil-m-38510/30105 | |
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Contextual Info: 8 < > M ilitary 54LS114A MOTOROLA Dual J -K Flip-Flop W ith P reset, Common C lear and Com m on C lock MPO MIL-M-38510/30105 unw The 54LS114A offers common clock and common clear inputs and individual J, K, and set Inputs. These monolithic dual flip-flops are |
OCR Scan |
54ls114amil-m-38510/30105jm38510/30105bxa54ls114a/bxa | |
SN54LS114A
Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
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sn54ls114asn54s114sn74ls114asn74s114a+2 | |
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Contextual Info: M M O T O R O M ilitary 54LS114A L A Dual J -K Flip-Flop W ith P reset, Com m on C lear and Com m on C lock M MIL-M-38510/30105 P O H U M The 54LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are |
OCR Scan |
54ls114amil-m-38510/30105jm38510/30105bxa | |
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Contextual Info: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK M A R C H 1973 — R E V ISE D M A R C H 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS114A . SN 54S114 |
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sn54ls114asn54s114sn74ls114asn74s114a+4 | |
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Contextual Info: 54LS114A. SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK _ MARCH 1973 —REVISED MARCH 1988 • Fully B u ffe re d to O ffe r M a x im u m Isolation |
OCR Scan |
sn54ls114asn54s114sn74ls114asn74s114a+3 | |
SN74ALS123
Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
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mil-m-38510sn74als123sn740174ls424+7 | |
SN54LS114A
Abstract: SN54S114 SN74 SN74LS114A SN74S114A
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sdls010sn54ls114asn54s114sn74ls114a+3 | |
74LS114AContextual Info: TYPES 54LS114A, SN54S114, SN74LS114A, SN74S114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK REVISED DECEMBER 1983 Fully Buffered to O ffer M axim um Isolation fro m External Disturbance S N 54L S 114A , S N 5 4 S 1 1 4 . . . J OR W PACKAGE |
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sn54ls114asn54s114sn74ls114asn74s114+1 | |
logos 4012B
Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
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OCR Scan |
tda1510tda1510alogos 4012b1lb553+8 | |
TSMC 0.18 um MOSfet
Abstract: M38510 10102BCA IDT7204L 5962-8768401MQA 0.18um LDMOS TSMC sl1053 TSMC 0.25Um LDMOS UT63M125BB SMD RTAX250S-CQ208 5962-04221
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Original |
qml-38535mil-prf-38535mil-std-790mil-std-690+11 |