540PS Search Results

ECL IC NAND

Contextual Info: sony CXB1501Q-Y . Quad 3-input AND/NAND Gate Description Pin Assignm ent The CXB1501Q-Y is an ultra high speed monolithic ECL IC, which contains our 3-input AND /NAND gates. 24 25 22 21 20 19 18 1? Features • Typical AC characteristics NC Q Tpd=540ps O iC

ECL IC NAND

Contextual Info: _ CXB1501Q-Y SONY. Quad 3-input AND/NAND Gate Description Pin Assignment The CXB1501Q-Y is an ultra high speed monolithic ECL IC, which contains four 3-input AND/NAND gates. NC 01 01 DI» O l i 01c D2» NC n Features • Typical AC characteristics Tpd=540ps

CH7318C-BF

Abstract: CH7318C CH7318C-BF-TR CH7318CBF HM12 MO-220 JESD-30 CH73
Contextual Info: CH7318C Chrontel CH7318C AC Coupled HDMI Level Shifter 1.0 FEATURES • • • • • • • • • • • • • • • • 2.0 GENERAL DESCRIPTION Converts low-swing AC coupled differential input to HDMI 1.3 compliant open-drain current steering Rx

A5700

Abstract: A295D A390C A295n A540PA A295B A390A A390B A540A A540B
Contextual Info: SILICON RECTIFIERS HIGH C URRENT 400-1500 AM PERES G E T Y P E A390A-PB A295A-PN A500P-LF' A540PA-L A570A-P ELECTRICAL S P EC IFIC A T IO N S Ifm a vj

Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS889831 LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS889831 is a high speed 1-to-4 Differentialto-LVPECL/ECL fanout buffer and is a member HiPerClockS

ICS889831

Abstract: ICS889831AK ICS889831AKT MO-220 SY89831U CML ECL termination common mode termination 50 Ohm
Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS889831 LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS889831 is a high speed 1-to-4 Differentialto-LVPECL/ECL Fanout Buffer and is a member HiPerClockS

max3678

Abstract: 3 phase automatic change over switch circuit diagram
Contextual Info: 19-4115; Rev 0; 5/08 EVALUATION KIT AVAILABLE Low-Jitter Frequency Synthesizer with Intelligent Dynamic Switching Features The MAX3678 is a low-jitter frequency synthesizer with intelligent dynamic clock switching optimized for systems where redundant clock failover switching is needed. It

Contextual Info: E ^ I V I I V I I I IV I vA T Ii □ H D -L IN X G S 1 5 0 4 H D TV A daptive Equalizer N ADVANCE INFORMATION NOTE FEATURES • SMPTE 292 M compliant • Automatic, adjustment free cable equalization for 1.485 Gb/s HDTV signals • Differential serial outputs capable of driving 50 £1

AN237 equivalent

Abstract: SMY02 5V996 AN-237 IDT5T2010 5T9110 5T9820 5T9821 5T9890 5T9891
Contextual Info: APPLICATION NOTE AN-237 PLL LOCK INDICATOR APPLICATION NOTE AN-237 PLL LOCK INDICATOR INTRODUCTION A PLL lock detector is implemented on the following device families: TurboClockII, TurboClockII Plus, TeraClock and Programmable Clock. The output of the lock detector is available on the LOCK pin. The lock circuitry

Contextual Info: Differential-to-LVDS Buffer/Divider with Internal Termination IDT8S89873I DATA SHEET General Description Features The IDT8S89873I is a high speed Differential-to-LVDS Buffer/Divider with Internal Termination. The IDT8S89873I has a selectable ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination

Sony

Abstract: QFP-24M-S01 CXB1501Q-Y OFP32 ECL IC NAND
Contextual Info: SONY CORP/COMPONENT PROÍS SDE D A3fl2303 0 0 0 3 R b b SONY. ISONY 4 CXB1501Q-Y Quad 3-input A N D /N A N D Gate Description Pin Assignment The C X B 1 5 0 1 Q -Y is an ultra high speed monolithic E C L 1C, which contains four 3-input A N D / N A N D gates.

CH7318C-BF

Contextual Info: CH7318C Chrontel CH7318C AC Coupled HDMI Level Shifter 1.0 FEATURES • • • • • • • • • • • • • • • • 2.0 GENERAL DESCRIPTION Converts low-swing AC coupled differential input to HDMI 1.4a compliant open-drain current steering Rx

CH7318C

Abstract: HDMI 1.4a ch7318c-bf CH7318CBF
Contextual Info: CH7318C Chrontel CH7318C AC Coupled HDMI Level Shifter 1.0 FEATURES • • • • • • • • • • • • • • • • 2.0 GENERAL DESCRIPTION Converts low-swing AC coupled differential input to HDMI 1.4a compliant open-drain current steering Rx

Contextual Info: Differential-to-LVDS Buffer/Divider with Internal Termination IDT8S89873I DATA SHEET General Description Features The IDT8S89873I is a high speed Differential-to-LVDS Buffer/Divider with Internal Termination. The IDT8S89873I has a selectable ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination