54 ACT 14 Search Results

Contextual Info: . February 1993 54AC/74AC109 • 54 ACT/74 ACT 109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’A C /’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

act 138

Contextual Info: & Semiconductor March 1993 54AC/74AC138 • 54 ACT/74 ACT 138 1-of-8 Decoder/Demultiplexer General Description Features The ’A C /’ACT138 is a high-speed 1-of-8 decoder/demulti­ plexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input

Contextual Info: February 1993 Semiconductor 54AC/74AC139 • 54 ACT/74 ACT 139 Dual 1-of-4 Decoder/Demultiplexer General Description Features The ’A C /’ACT139 is a high-speed, dual 1-of-4 decoder/de­ multiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-LOW outputs. Each decoder has an activeLOW Enable input which can be used as a data input for a

74ACT2726

Contextual Info: 2726 National Semiconductor ADVANCE INFORMATION 54 ACT /7 4ACT2726 512 x 9 Bidirectional First In, First Out Memory BIFIFO General Description Features The 512 x 9 FIFO is a first-in, first-out dual port memory capable of asynchronous, simultaneous read and write. Oth­

Contextual Info: DR/4W1NG THIS MA DE DRAWI NG IN 4 THIRD ANGLE IS UNPUBLISHED. COPYRIGHT 19 <Z> PROJECTION RELEASED FOR PUBLICATION BY AMP INCORPORATED. ALL INTERNATIONAL LOC CM RIGHTS RESERVED. DIST 54 REVISIONS ZONE LTR DESCRIPTION DATE APPD RE/ACT-2, -4, -5, -7 THRU - 1 4 , - 1 6 THRU

A300

Abstract: C021
Contextual Info: CATALOGUE L I S T I N G LIMIT S W IT C H Dü dqd saw ©ÖO FIG. 1 41 (1.62 34 (1.34) 0) I -I I h s GLS CHART NO. MTG-GL-194 13 O S N A P -A C T IO N C O N TA C TS S L O W - ACT I ON C O N TA C TS MAKE BEFORE BREAK 54° to 75' 24.75 (.974) 0‘ 21-22 13-14

54ACT112

Abstract: ACT112 E20A J16A
Contextual Info: S e p te m b e r 1 9 9 8 54 ACT 112 Dual JK Negative Edge-Triggered Flip-Flop General Description A s y n c h ro n o u s Inputs: T h e ’A C T 1 1 2 c o n ta in s tw o in d e p e n d e n t, h ig h -s p e e d J K flip -flo p s w ith D ire c t S e t a n d C le a r in p u ts . S y n c h ro n o u s s ta te

Contextual Info: Integrated Circuit Systems, Inc. ICS9150-11 Pentium Pro and SDRAM Frequency Generator Features General Description Generates five processor, six bus, one 14.31818MHz and 16 SDRAM clocks. Synchronous clocks skew matched to 250 ps window on PCLKs and 500ps window on BCLKs

74ACT244 HARRIS

Abstract: 74ACT244 harris semiconductor
Contextual Info: Technical D a t a _ CD54/74AC240/241 /244 CD54/74ACT240/241 /244 241 A 244 240 18 1 YO 1 YO 16 1Y1 1Y1 14 1 AO 1A1 1A2 1Y2 TŸ2 12 1A3 9 2YO 2Ÿ0 7_ 2Y1 2Ÿ1 5 2Y2 2Ÿ2 2A0 2A1 2A2 3 2 A3 240 & 244 1Y3 Ο3 241 Type Features: • B uffered inputs

cd74ac280

Abstract: 74ac280
Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker £ EVEN X ODD Type Features: NC« 3 3 ZCS- 3 M VCC "14 • B uttered inputs ■ Typical propagation delay: 10 ns @ Vtx - 5 V, T„ = 25°C, C l = 50 pF 6 NO* ? FUNCTIONAL DIAGRAM

Contextual Info: Integrated Circuit Systems, Inc. ICS9148-11 Frequency Generator & Integrated Buffers for PENTIUM General Description Features Generates four processor, six bus, one 14.31818MHzand 12 SDRAM clocks. Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on BUS clocks.

KV149

Abstract: KV1480 KV1471 KV1530 610D KV1420 KV1430 KV1440 KV1450 KV1460
Contextual Info: - 194 - £ ft Vrm Vr mV (V) (V) min 100 30 39. 79 24. 25 17. 32 13.93 69.14 43.09 25. 05 15. 44 43 * m £ tt K V 14 20 P £ Tun * KV1430 Tun 100 18 KV1440 Tun 100 18 KV1450 Ä5t KV1460 fdmax S Ä J t Ct (Vl)/Ct (V2) awismtt mm m Ct,Cj*(pF) Tun 100 18 Tun

Contextual Info: Direct RDRAM K4R271669B/K4R441869B 128/144Mbit RDRAM B-die 256K x 16/18 bit x 32s banks Direct RDRAMTM Version 1.11 October 2000 Page -1 Version 1.11 Oct. 2000 Direct RDRAM™ K4R271669B/K4R441869B Change History Version 1.11 ( October 2000) - Preliminary

is42s164008

Contextual Info: ISSI IS42S16400 1 Meg Bits x 16 Bits x 4 Banks 64-MBIT SYNCHRONOUS DYNAMIC RAM TARGET SPECIFICATION JUNE 2000 FEATURES DESCRIPTION • Clock frequency: 166, 143, 125, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge

he71

Contextual Info: Technical Data —-— —- CD54/74AC257, CD54/74AC258 CD54/74ACT257, CD54/74ACT258 257 2 1'o 210 3 '0 41O 11 2*1 *311 411 S 2 58 5 11 1Y TŸ 14 3 6 2Y 2Ÿ 3Y 3Ÿ Quad 2-Input Multiplexer with 3-State Outputs CD54/74AC/ACT257 - Non-Inverting Outputs

Contextual Info: HARRIS SEMICOND Technical Data SECTOR 37E D 43Q2S71 GDSSMSb ô BHAS* _ C D54/74AC164 C D 54/74A C T164 00 Q1 02 03 04 Advance Information 8-Bit Serial-In/Parallel-Out Shift Register 05 0« 07 MRCP- Vcc 3 14 G ND=7 92CS-38499 Type Features:

e61 marking code

Contextual Info: Direct RDRAM K4R271669A/K4R441869A 128/144Mbit RDRAM A-die 256K x 16/18 bit x 32s banks Direct RDRAMTM Version 1.11 October 2000 Page -1 Version 1.11 Oct. 2000 Direct RDRAM™ K4R271669A/K4R441869A Change History Version 1.0 ( July 1999 ) - Preliminary

W981204BH

Contextual Info: Preliminary-W981204BH 8M x 4 BANKS × 4 BIT SDRAM GENERAL DESCRIPTION W981204BH is a high-speed synchronous dynamic random access memory SDRAM , organized as 8M words × 4 banks × 4 bits. Using pipelined architecture and 0.175 µm process technology, W981204BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the

74173

Contextual Info: - 74173 14 I - 4-B it Register 3-State r 1» H *•M 1* H •'U ' 1 10 2D 30 40 0 UTPUT a NTROL 10 CLEAR 20 30 4Q □ DATA ENABLE r„ CK A OUTPUT CONTROL OUTPUTS ms 1} A C le a r E n ab le L L H _ n _ IS G 1 G 2 L L H X X H X X M N X & Qd 1 D — 4D - - -

74243

Abstract: 74LS621 74LS623
Contextual Info: Quad 3-State Bus Transceivers 8 bit S f i t l t 74LS621, 74LS623 iy h & ms * 'J ' A ? tpd «ax L-H tpd max H-*L T i 18 11 11 6 .2 9 6. 5 9 tpd max Z— L V 30 20 21 8.5 15 tpd max Z-*H A 23 20 19 6. 7 12 tpd nax L-Z T 25) 22 8 7 tpd nax H-*Z ▲ (18) 14

vhdl code for data memory

Abstract: palasm
Contextual Info: 39056_1b.frm Page 1 Friday, March 14, 1997 8:54 AM 3.1.1 Supplement for ACTmap VHDL Synthesis This document describes the new features of the ACTmap VHDL Synthesis tool. It also contains important information about the software, including information from the previous 3.1 release that

TCMS

Abstract: W982504BH W982504BH-75
Contextual Info: W982504BH 16M x 4 BANKS × 4 BIT SDRAM GENERAL DESCRIPTION W982504BH is a high-speed synchronous dynamic random access memory SDRAM , organized as 16M words × 4 banks × 4 bits. Using pipelined architecture and 0.175 µm process technology, W982504BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the

20t201

Abstract: ic 74190 74190 74191 74191 8 bit counter 74190 f ic 74190 BCD counter IC 74LS190 74190 counter
Contextual Info: - 149 - Presettable synchronous Up/D ow n BCD Counter 74190 A CLOCK CLOCK At ENABLE DOWN/ < OUTPUTS INPUTS o 4 bit ib im ä t y - r r <7 -9 u /d -w i y io 9 ') T S i i ' L o ffi)H £ lc o v > T lil6 0 « * # » . m ff » M n n Load D/ Ü H L H H CK m n -

da53

Abstract: 144MD-50-711 144MD-53-600 128MD-40-800 128MD-50-711 128MD-53-600 144MD-40-800
Contextual Info: Direct RDRAM RAMBUS 128/144-Mbit 256Kx16/18x32s Preliminary Information Overview The Rambus Direct RDRAM™ is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application