54/74 TTL SERIES Search Results

AND-OR-INVERT gate

Abstract: 74 series family 74 series inverter
Contextual Info: BIPOLAR DIGITAL ICs continued •o 4->a 5 D Q. • PACKAGE C FANOUT DESCRIPTION TYPE TTL-T 74 H, T 54 H series" T 74/54 H 00 Quad 2-input positive NAND gate 6 90 10 T 74/54 H 04 Hex inverter 8 140 10 DIP H,P DIP H,P T 74/54 H 05* Hex inverter w ith open collector

SLCS008A

Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SICS008A - OCTOBER 1979 - REVISED OCTOBER 1991 Fast Response Times D OR P PACKAGE TOP VIEW Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability GND [ IN+ [ IN - [ Short-Circuit and Surge Protection

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gates 74LS series logic gate symbols 74ls gate symbols 74125 ic 74LS126 74LS55 r025 74LS125 74LS51
Contextual Info: FAIRCHILD DIGITAL TTL High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram 2 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW Low Power Schottky 54LS/74LS 5 ns/2 mW Item 9000 Series 8 ns/10 mW (Cont'd) Function’11 SSI FUNCTIONS 5 't/I

Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A − OCTOBER 1979 − REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

LM306 application

Abstract: lm306p
Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A – OCTOBER 1979 – REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

LM306

Abstract: LM306D LM306DE4 LM306DG4 LM306DR LM306DRE4 LM306DRG4 LM306P LM306PE4
Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A − OCTOBER 1979 − REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

LM306

Abstract: LM306D LM306P SLCS008A
Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A – OCTOBER 1979 – REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A − OCTOBER 1979 − REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A − OCTOBER 1979 − REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

Contextual Info: LM306 DIFFERENTIAL COMPARATOR WITH STROBES SLCS008A – OCTOBER 1979 – REVISED OCTOBER 1991 D D D D D D D OR P PACKAGE TOP VIEW Fast Response Times Improved Gain and Accuracy Fanout to 10 Series 54/74 TTL Loads Strobe Capability Short-Circuit and Surge Protection

Z427

Abstract: FL 9014 TTL 7409 TTL 7486 74LS32 74ls86 TTL 74s32 74LS08 74LS11 74LS02
Contextual Info: FAIRCHILD DIGITAL TTL SSI FUNCTIONS Cont’d X to x n agic/Conne Diagram igh Speed 54H/74H ns/22 mW O IO U) —1 ligh Speed Schottky 54S/74S ns/19 mW CO Std. TTL 54/74 1 ns/10 mW E a> Dw Power Schottky ILS/74LS ns/2 mW ~'c o u c 3 U. 9000 Series ns/10 mW

74LS08 Quad 2-Input AND Gates

Abstract: TTL 74s32 TTL 7408 or 2 input 74Ls32 74LS11 and 74LS32 74ls32 quad 2-input OR gates 54LS TTL 7421 74LS 3-input NOR 74LS11
Contextual Info: FAIRCHILD DIGITAL TTL High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram'2’ E £ Std. TTL 54/74 10 ns/10 mW ~c o o c S U. Low Power Schottky 54LS/74LS 5 ns/2 mW Cont’d 9000 Series 8 ns/10 mW SSI FUNCTIONS 5

74123A

Abstract: S54123 S-5412 74123 time delay 74123
Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W 74 PIN CONFIGURATION B,F B,F,W PACKAGE DESCRIPTION These monolithic TTL retriggerable monostable multivibrators fea­ ture dc triggering from gated low-level-active A and high-levelactive (B) inputs, and also provide overriding direct clear inputs.

Contextual Info: 03 ! I LM106, LM206, LM306 DIFFERENTIAL COMPARATORS WITH STROBES J • Fast Response Times J OR N DUAL-IN-LINE OR W FLAT PACKAGE • Improved Gain and Accuracy • Fan-Out to 10 Series 54/74 TTL Loads TOP VIEW • Strobe Capability • Short-Circuit and Surge Protection

TTL 74ls125

Abstract: 74ls125 74125 logic diagram 74LS126 74LS366 74ls368
Contextual Info: FAIRCHILD DIGITAL TTL Logic/Connection Diagram 2 Packages(3) 9386 (8242) D94 3I,6A,9A D25 4L,6B,9B — D26 3I,6A,9A — D27 3I,6A,9A 54S/74S51 D28 3I,6A,9A High Speed Schottky 54S/74S 3 ns/19 mW 74LS266 High Speed 54H/74H 6 ns/22 mW Std. TTL 9N 54/74 10 ns/10 mW

N74416

Abstract: N7441 74 TTL series 24V decoder IC
Contextual Info: s ig n o tic s BCO-TO-OECtMAL DECODER/DRIVER DIGITAL 54/74 TTL SERIES D E S C R IP T IO N PIN CO N FIG U R A T IO N The N74416 Nixie* Decoder/Driver it • on»-out-oMen decoder which has been designed to provida th« necessary high voltage characteristics required for driving get-filled cold-cathode indicator

N7441B

Abstract: ttl 7441 74 TTL series BURROUGHS N7441 7441 74TTL
Contextual Info: s ig n o t ic s BCD-TO-DECIMAL DECODER/DRIVER I ^ 7 4 4 ] N7441B DIGITAL 54/74 TTL SERIES D E S C R IP T IO N T h e N 7 4 4 1 6 N ix ie * D ecoder/D river is • o n e -o u t-o f-ten decoder w hich has b«tn designed to provide the n s e n u r y high voltage

DM9000C

Abstract: "Pin for Pin" 400S 9003C DM7410 Fairchild 9003
Contextual Info: DM9003C National ÆÜASemiconductor \ DM9003C Triple 3-Input NAND Gates General Description Fo r th e new d e s ig n s , th e 54/74 fa m ilie s o f TTL c irc u its o f­ fe r th e in d u s try 's b ro a d e s t c h o ic e o f h ig h -p e rfo rm a n c e d ig ita l c irc u its . S eries 54774 p in -fo r-p in e q u iv a le n t is

74LS623

Abstract: SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUT The SN54 / 74LS623 series is an octal bus transceiver designed for asynchronous two-way communication between data buses. Control function implementation allows maximum timing flexibility. Enable inputs may be used

74LS623

Abstract: SN54LSXXXJ SN74LSXXXN A3126 GAB20 8A79
Contextual Info: SN54/74LS623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUT The SN54 / 74LS623 series is an octal bus transceiver designed for asynchronous two-way communication between data buses. Control function implementation allows maximum timing flexibility. Enable inputs may be used

74ls795

Abstract: 81LS95 74LS796 74LS798 81LS98 LS795 SN54/74LS797
Contextual Info: SN54/74LS795 SN54/74LS796 SN54/74LS797 SN54/74LS798 TRI-STATE OCTAL BUFFERS The SN54 / 74LS795 thru SN54 / 74LS798 device types provide a second source for the 71 / 81LS95 thru 71 / 81LS98 series. These devices are octal low power Schottky versions of the 70/8095 thru 70/8098 3-STATE Hex

function of latch ic 74373

Abstract: full adder using ic 74138 pins and their function in ic 74163 encoder IC 74147 74373 cmos dual s-r latch sn 74373 74373 latch ic 74541 buffer MSM7000 MSM70000
Contextual Info: • GENERAL DESCRIPTION The M S M 7 0 0 0 0 series is the gate array L S I based on the master slice method using the high performance silicon gate H C M O S process with the dual-layer metal structure. This series has the features to easily realize functions-of the schm itt trigger, crystal/

PCS-E68LKPB

Abstract: MARKING 1BW PCS-E68LK
Contextual Info: Frame grabber cables A8406 series Various types of cables for frame grabber A8406-42 A flat panel sensor adopting parallel video output requires a frame grabber cable for transmitting the digital video data to a frame grabber card installed in PC. Frame grabber cables A8406 series are cables that connect the flat panel sensor to a frame grabber.

74138n

Abstract: buffer 74374 74373 cmos dual s-r latch of IC 74191 G701
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 H 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm a n c e silicon gate 2 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T h is series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/