512 X 4 PROM Search Results

A01 monolithic amplifier

Abstract: A02 monolithic amplifier CCD LINEAR SENSOR 512 CCD linear array A03 monolithic amplifier CCD412A Loral linear image sensor transparent substrate Contact image sensor fairchild
Contextual Info: LDRAL Fairchild Im aging Sensors C C D 4 1 2 A 512 x 512 Element Full Frame Image SenSOf FEATURES • 512 x 512 Photosite Array ■ 1£^m x 1£pim Pixel ■ 7.68mm x 7.68 mm Image Area ■ 100% Fill Factor ■ Multi-Pinned Phase MPP Option ■ Readout Noise Less Than 7 Electrons at 250k pixels/ sec

Contextual Info: V58C2512 804/404/164 SD HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 75 DDR500 DDR400 DDR333 DDR266 Clock Cycle Time (tCK2) - 7.5ns 7.5ns - Clock Cycle Time (tCK2.5) - 6ns 6ns 7.5ns

DIN 13715

Abstract: 12197-507-XTD AMIS41683CANN1G N08L6182AB27I FS7145-02G-XTD valve positioners 11640-843-XTP vending machine fuji SEOUL 5630 LED DATASHEET 19699-002-XTP
Contextual Info: Ultra-Low Power SRAMs Density Mb Organization Voltage Range Speed (ns) Features Package N08L6182A Part Number 8 512 Kb x 16 1.65 - 2.2 70 Dual CE 48-BGA N08L63W2A 8 512 Kb x 16 2.3 - 3.6 70 Dual CE 48-BGA N04L63W2A 4 256 Kb x 16 2.3 - 3.6 55 Dual CE 44-TSOP2, 48-BGA

Contextual Info: V58C2512 804/404/164 SA HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time (tCK2.5) 4.5ns 6ns 6ns Clock Cycle Time (tCK3) 4.5ns 5ns - Clock Cycle Time (tCK4)

Contextual Info: V58C2512 804/404/164 SB*I 512 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 6 75 DDR400 DDR333 DDR266 Clock Cycle Time (tCK2.5) 6ns 6ns 7.5ns Clock Cycle Time (tCK3) 5ns - - 200 MHz

Contextual Info: V58C2512 804/404/164 SA HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time (tCK2.5) 5ns 5ns 6ns Clock Cycle Time (tCK3) 4ns 5ns - 250 MHz 200 MHz

DM74S571

Abstract: DM74S571N DM74S571V J16A N16A programming TiW PROMs DM74S571J
Contextual Info: DM74S571 S3 National ÆÆ Semiconductor DM74S571 512 x 4 2048-Bit TTL PROM General Description Features This S chottky m em ory is organized in the popular 512 w ords by 4 bits configuration. A m em ory enable input is pro­ vided to control th e output states. W hen the device is en­

v59c1512

Contextual Info: PRELIMINARY V59C1512 404/804/164 Q HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: V58C2512 804/404/164 SD HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 75 DDR500 DDR400 DDR333 DDR266 - 6ns 6ns 7.5ns 4ns 5ns - - 250 MHz 200 MHz 166 MHz 133 MHz Clock Cycle Time (tCK2.5)

V58C2512

Contextual Info: V58C2512 804/404/164 SD*I 512 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 75 DDR500 DDR400 DDR333 DDR266 - 6ns 6ns 7.5ns 4ns 5ns - - 250 MHz 200 MHz 166 MHz 133 MHz Clock Cycle Time (tCK2.5)

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

v58c2512

Abstract: V58C251 V58C25
Contextual Info: V58C2512 804/404/164 SB HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 6 75 DDR400 DDR333 DDR266 Clock Cycle Time (tCK2.5) 6ns 6ns 7.5ns Clock Cycle Time (tCK3) 5ns - - 200 MHz 166 MHz

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: V58C2512 804/404/164 SB HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 6 75 DDR400 DDR333 DDR266 Clock Cycle Time (tCK2.5) 6ns 6ns 7.5ns Clock Cycle Time (tCK3) 5ns - - 200 MHz 166 MHz

Contextual Info: V58C2512 804/404/164 SD HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 4 5 6 75 DDR500 DDR400 DDR333 DDR266 - 6ns 6ns 7.5ns 4ns 5ns - - 250 MHz 200 MHz 166 MHz 133 MHz Clock Cycle Time (tCK2.5)

Contextual Info: V58C2512 804/404/164 SB HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 6 75 DDR400 DDR333 DDR266 Clock Cycle Time (tCK2.5) 6ns 6ns 7.5ns Clock Cycle Time (tCK3) 5ns - - 200 MHz 166 MHz

Contextual Info: PRELIMINARY V59C1512 404/804/164 QA HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4) 5ns 3.75ns

Contextual Info: H A RR IS S E H I C O N D S E C T O R 4bE ]> • 4 3 G 2 2 7 1 DD3=]237 D ■ HAS HM-6642 ÊE X - H îq - I^ - Z S 512 X 8 CMOS PROM January 1992 Features Description • Low Power Standby and Operating Power The HM-6642 is a 512 x 8 CMOS NiCr fusible link

Contextual Info: V58C2512 804/404/164 SA*I HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz

Contextual Info: V58C2512 804/404/164 SA HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz

Contextual Info: V59C1512 404/804/164 QA*I HIGH PERFORMANCE 512 Mbit DDR2 SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) PRELIMINARY 5 37 3 DDR2-400 DDR2-533 DDR2-667 Clock Cycle Time (tCK3) 5ns 5ns 5ns Clock Cycle Time (tCK4)