5065M Search Results

c2xxx

Abstract: PL611-20 marking code sot-23 697 marking code sot23 697
Contextual Info: PL611-20 Programmable Quick Turn Clock T M FEATURES • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN/FIN 3 PL611-20 • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical

Contextual Info: PL611-01 Programmable Clock T M FEATURES •  XIN,FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,PDB,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN, FIN 3 PL611-01    Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical

PL611-30

Abstract: P611-30
Contextual Info: Preliminary Programmable Quick Turn Clock T M FEATURES PIN CONFIGURATION • Advanced programmable PLL design  Very low Jitter and Phase Noise < 40ps Pk-Pk typ.  Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs.  Output Frequencies:

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL Clock Drivers, 3 -S ta te 55, 70, 100, 133 and 160MHz Versions The MC88915T Clock Driver utilizes phase-locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference

Contextual Info: MO TO R O L A SC LOGIC b3E D • b 3 b ? 2 S S □DTB'lOb A 4 2 « M O T M MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL C lock D river W ith Processor R eset Features • Provides Performance Required to Drive 68030 Microprocessor Family as well as the 33 and 40MHz 68040 Microprocessors

PL611-31

Abstract: p611 31-XXX
Contextual Info: Programmable Quick Turn Clock T M FEATURES •          PIN CONFIGURATION Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Up to 3 outputs Output frequency up to 200MHz CMOS. o Provides complementary LVCMOS outputs to

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information Low S kew CMOS PLL C lock Drivers, 3 -S tate 55, 70, 100, 133 and 160M H z Versions The MC88915T Clock Driver utilizes phase-locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference

OHD 3- 80M

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL C lock Drivers, 3 -S ta te 55, 70, 100, 133 and 160M Hz Versions The M C 88915T C lock D river utilizes p h a se -lo cke d loop technology to lock its low skew o utputs’ fre q u en cy and phase onto an input reference

PL611-30

Contextual Info: Preliminary PL611-30 Programmable Quick Turn Clock T M PIN CONFIGURATION FEATURES • • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Output frequency up to 375MHz CMOS. Supports differential CMOS output to produce PECL,

ABPX1101-XXXSC

Abstract: ABPX1101-XXXMC ABPX1101-XXXSC-T abracon programming 3digit up down counter A1XXX
Contextual Info: ABPX1101 Advanced Programmable Clock FEATURES • • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,PDB,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK0 1 GND 2 XIN/FIN 3 ABPX1101 • • Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical

ABPX1130-XXXSC

Abstract: ABPX1130-XXXMC ABPX1130-XXXSC-T APBX1130-XXX abracon programming
Contextual Info: Preliminary ABPX1130 Advanced Programmable Clock FEATURES • • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Output frequency up to 375MHz CMOS. Supports differential CMOS output to produce PECL, LVDS XIN/FIN

Super Capacitor Charger

Abstract: igbt dc to dc converter capacitor charging capacitor 1 micro farad / 16 volts Electrolytic xenon flashlight driver how to make a Super Capacitor 3.7V Li-Ion battery charge controller with 5v inp 100 micro farad capacitor super cap 5.5v SUPER CAPACITOR k800i
Contextual Info: APPLICATION NOTE AN-130 Storing Power with Super Capacitors A EC D T VA TO NC CH ED AN IN F G O E R W MA IT HO TIO UT N NO TI C E Portable system designers have sharply reduced the power requirements of their systems in active and standby mode over the last several years, a growing number of applications pose an entirely different problem. Some of the most

202377A

Contextual Info: APPLICATION NOTE Storing Power with Super Capacitors Storing Power with Super Capacitors Portable system designers have sharply reduced the power requirements of their systems in active and standby mode over the last several years, a growing number of applications pose an entirely different problem. Some of the most

Sprecher Schuh LE 2-16

Abstract: Sprecher Schuh CS1 Sprecher Schuh timer Sprecher Schuh LE 2-20
Contextual Info: G Control & Timing Relays Control & Timing Relays CS7 Industrial Control Relays. G2 Technical Information. G17

Contextual Info: ABPX1120 Advanced Programmable Clock FEATURES • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN/FIN 3 ABPX1120 • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL Clock Driver W ith Processor Reset The MC88916 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor

PL611-01

Abstract: PL611-01-XXXMC PL611-01-XXXSC dd marking
Contextual Info: Programmable Quick Turn Clock T M FEATURES •          PIN CONFIGURATION Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical Up to 3 programmable outputs Output frequency up to 200MHz CMOS. Accepts Crystal or reference clock inputs

ARM720T

Abstract: ARM740T ARM7 ISA ARM7 characteristics ARM10 ARM710T ARM920T ARM940T EPOC32 ARM Holdings plc
Contextual Info: プロダクトインフォメーション ARM7 Thumb™ファミリ ARM7TDMI™ARM7TDMI-S™、ARM720T™、ARM740T™ ARM7™Thumb™ファミリは、価格と消費電力が重視される民生用 アプリケーション向けに最適化された低消費電力32ビットRISCマ

XTAL 50MHZ

Abstract: PL611-25 RS-30 24V
Contextual Info: PL611-25 Programmable Quick Turn Clock T M FEATURES PAD LAYOUT AND DIE ID • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Two registers banks for 2-time programming. Output frequency up to 200MHz CMOS.

PL611-01

Abstract: marking code PDB PL611-01-XXXMC PL611-01-XXXSC
Contextual Info: PL611-01 Programmable Quick Turn Clock T M FEATURES • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,PDB,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN/FIN 3 PL611-01 • • • Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical

Sprecher Schuh

Abstract: Sprecher Schuh timer Sprecher Schuh L 2-20 sprecher iec 947 -3
Contextual Info: RZ7-FS Electronic Timing Relays Precision DIN-rail mounted timing relays for any industrial application RZ7 Timing Relays G Sprecher + Schuh’s new RZ7-FS precision electronic timing relays offer 19 different output functions applicable to all types of industrial control. In

C8891

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low S kew CMOS PLL C lock Driver W ith Processor R eset The MC88916 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor