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    50-PIN LVDS Search Results

    50-PIN LVDS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-002.5
    Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-002.5 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft PDF
    CS-DSDMDB09MM-025
    Amphenol Cables on Demand Amphenol CS-DSDMDB09MM-025 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft PDF
    CS-DSDMDB15MM-005
    Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-005 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 5ft PDF
    CS-DSDMDB25MF-50
    Amphenol Cables on Demand Amphenol CS-DSDMDB25MF-50 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Female 50ft PDF
    CS-DSDMDB37MF-015
    Amphenol Cables on Demand Amphenol CS-DSDMDB37MF-015 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Female 15ft PDF

    50-PIN LVDS Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    6-pin "454"

    Contextual Info: CY2XF33 High-Performance LVDS Oscillator With Frequency Margining – Pin Control Features Functional Description • Low jitter crystal oscillator XO ■ Less than 1 ps typical RMS phase jitter ■ Differential LVDS output ■ Output frequency from 50 MHz to 690 MHz


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    CY2XF33 CY2XF33 6-pin "454" PDF

    Contextual Info: NB3L14S 2.5 V 1:4 LVDS Fanout Buffer The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. The NB3L14S LVDS signals will be buffered and replicated to identical LVDS copies of the Input


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    NB3L14S NB3L14S NB3L14S/D PDF

    SN65LVDS049

    Abstract: C101 DS90LV049 SN65LVDS049PW SN65LVDS049PWG4
    Contextual Info: SN65LVDS049 5,0 mm x 6,4 mm www.ti.com SLLS575 – AUGUST 2003 DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS FEATURES • • • • • • • • • • • • • • DS90LV049 Compatible Up to 400 Mbps Signaling Rates Flow-Through Pin-out 50 ps Driver Channel-to-Channel Skew Typ


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    SN65LVDS049 SLLS575 DS90LV049 TIA/EIA-644-A 16-pin SN65LVDS049 C101 SN65LVDS049PW SN65LVDS049PWG4 PDF

    Contextual Info: SN65LVDS049 5,0 mm x 6,4 mm www.ti.com SLLS575 – AUGUST 2003 DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS FEATURES • • • • • • • • • • • • • • DS90LV049 Compatible Up to 400 Mbps Signaling Rates Flow-Through Pin-out 50 ps Driver Channel-to-Channel Skew Typ


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    SN65LVDS049 SLLS575 DS90LV049 TIA/EIA-644-A 16-pin PDF

    Contextual Info: SN65LVDS049 5,0 mm x 6,4 mm www.ti.com SLLS575 – AUGUST 2003 DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS FEATURES • • • • • • • • • • • • • • DS90LV049 Compatible Up to 400 Mbps Signaling Rates Flow-Through Pin-out 50 ps Driver Channel-to-Channel Skew Typ


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    SN65LVDS049 SLLS575 DS90LV049 TIA/EIA-644-A 16-pin PDF

    MC100EP16T

    Abstract: MC10EP16T
    Contextual Info: MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin


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    MC10EP16T, MC100EP16T EP16T HEP61ws MC10EP16T/D MC100EP16T MC10EP16T PDF

    TC4-19

    Abstract: SPC15354 CC0805K GRM188F51C224ZA01D C3216X5R1C106M LMH6554LE CC0805KRX7R7BB104 TNPW040249R9BEED SPC15182 TNPW040249R9BEE
    Contextual Info: National Semiconductor Application Note 1945 Vannavong Philavanh June 29, 2010 General Description RL*4 , where RL is the impedance from pin 4 of the transformer to the load. For example, if RL = 50Ω for the test equipment, to achieve an impedance of 500Ω seen by the


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    LMH6554 LMH6554LE-EVAL AN-1945 TC4-19 SPC15354 CC0805K GRM188F51C224ZA01D C3216X5R1C106M LMH6554LE CC0805KRX7R7BB104 TNPW040249R9BEED SPC15182 TNPW040249R9BEE PDF

    ET5028-50

    Abstract: et1310 switch SGMII
    Contextual Info: Product Brief February 2006 ET5048-50 Single-Chip 48 x 1 Gbit/s Layer 2/3 Ethernet Switch Q Q Q Q Q Features Q Q Forty-eight 10/100/1000 Mbits/s Ethernet ports: — Forty-four-port, 6-pin SGMII interfaces to GbE copper PHYs — Four combo ports supporting either SGMII interface or


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    ET5048-50 PB06-026GSWC ET5028-50 et1310 switch SGMII PDF

    SFP EVALUATION BOARD 10G

    Abstract: et-412
    Contextual Info: Product Brief February 2006 ET5128-50 Single-Chip 28 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2/3 Ethernet Switch Q Q 1 Q Q Q Features Q Q Q Twenty-eight 10/100/1000 Mbits/s Ethernet ports: — Twenty-four-port, 6-pin SGMII interfaces to GbE copper PHYs — Four combo ports supporting either SGMII interface or


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    ET5128-50 PB06-031GSWC SFP EVALUATION BOARD 10G et-412 PDF

    tpl 550

    Abstract: 74AHC 74VHC ADCMP601 ADCMP604 ADCMP605 ADCMP605BCPZ jedec MO-203 ab
    Contextual Info: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators ADCMP604/ADCMP605 Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage 1.6 ns propagation delay


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    ADCMP604/ADCMP605 ADCMP605 ADCMP604/ ADCMP605 12-Lead CP-12-1 tpl 550 74AHC 74VHC ADCMP601 ADCMP604 ADCMP605BCPZ jedec MO-203 ab PDF

    Oscillator, 3.3Vdc PECL

    Contextual Info: Model 635 LVPECL or LVDS CLOCK OSCILLATOR FEATURES • • • • • • • • • • • Standard 7.5x5.0mm Surface Mount Footprint Differential LVPECL or LVDS Output Fundamental or Overtone Crystal Low Phase Jitter Frequency Range 19.44 – 250 MHz


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    2x10-8 J-STD-020. Oscillator, 3.3Vdc PECL PDF

    CY2DL818

    Abstract: CY2DL818ZC CY2DL818ZCT CY2DL818ZI CY2DL818ZIT
    Contextual Info: CY2DL818 1:8 Clock Fanout Buffer Features Low voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVDS Outputs Drives either a 50-ohm or 100-ohm load selectable Low input capacitance Low output skew Low propagation delay


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    CY2DL818 50-ohm 100-ohm 35-micron CY2DL818 CY2DL818ZC CY2DL818ZCT CY2DL818ZI CY2DL818ZIT PDF

    Contextual Info: FEATURES Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage Propagation delay: 1.6 ns Power dissipation: 37 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch


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    AD8465 CP-12-3) AD8465WBCPZ-WP AD8465WBCPZ-R7 12-Lead 010809-B CP-12-3 CP-12-3 PDF

    1G07

    Abstract: 74AHC 74VHC ADCMP601 CP123
    Contextual Info: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparator AD8465 Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage Propagation delay: 1.6 ns Power dissipation: 37 mW at 2.5 V


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    AD8465 12-Lead CP-12-3) AD8465WBCPZ-WP AD8465WBCPZ-R71 CP-12-3 1G07 74AHC 74VHC ADCMP601 CP123 PDF

    Contextual Info: CY2DL818 1:8 Clock Fanout Buffer Features Low voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVDS Outputs Drives either a 50-ohm or 100-ohm load selectable Low input capacitance Low output skew Low propagation delay


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    CY2DL818 50-ohm 100-ohm 35-micron CY2DL818 PDF

    Contextual Info: Model 658 CLOCK, HIGH FREQUENCY MULTIPLIER FEATURES • • • • • • • • • • Standard 7x5mm Surface Mount Footprint LVCMOS, Differential LVPECL or LVDS Outputs Frequency Range 38 – 750 MHz Frequency Stability, ±50 ppm Standard ± 25 ppm and ± 100 ppm available


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    2x10-8 J-STD-020. PDF

    Contextual Info: ADS6225, ADS6224 ADS6223, ADS6222 w w w .t i.c om SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007 DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE • FEATURES 1 • • • • • • • • • • Maximum Sample Rate: 125 MSPS


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    ADS6225, ADS6224 ADS6223, ADS6222 SLAS543A 12-BIT, 12-Bit ADS6225 ADS6224 ADS6223 PDF

    Contextual Info: PECL, LVDS, OCXO Page 1 - 7 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products Differential PECL Series Differential PECL Output, Some with Enable/ Disable Function Available in 9 Different Package/Configurations, See Next Pages


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    Contextual Info: Model 335 DIFFERENTIAL LVPECL AND LVDS VCXO FEATURES • • • • Standard 7x5mm Surface Mount Footprint Differential LVPECL or LVDS Outputs Frequency Range 19.44 – 212.50 MHz Frequency Stability, ±50 ppm Standard ± 25 ppm available • +2.5Vdc or +3.3Vdc Operation


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    2x10-8 J-STD-020. PDF

    Contextual Info: ADS5546 www.ti.com SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007 14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • • • • • Maximum Sample Rate: 190 MSPS


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    ADS5546 SLWS183D 14-BIT, 14-Bit 70-MHz 87-dBc PDF

    Contextual Info: MAP, MAL, and MAV Series ¾ Industry Standard Package ¾ Wide Frequency Range ¾ RoHS Compliant Available ¾ Less than 1 pSec Jitter ELECTRICAL SPECIFICATION: LVDS LVPECL PECL 12.500MHz to 800.000MHZ See Part Number Guide for Options (See Part Number Guide for Options)


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    500MHz 000MHZ 10mSec MAP060607H PDF

    Contextual Info: CDCUN1208LP www.ti.com SCAS928 – MAY 2012 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES • 1 • • • • 2 Configuration Options via pins or SPI/I C : – Input Type (HCSL, LVDS, LVCMOS)


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    CDCUN1208LP SCAS928 10kHz-20MHz) 100MHz PDF

    50 Ohm Termination pad

    Contextual Info: PECL, LVDS, OCXO Page 1 - 7 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products LV7645D LVDS Series Low Voltage Differential Signal Output with Enable / Disable 80.00 MHz – 212.50 MHz


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    LV7645D 50 Ohm Termination pad PDF

    50 Ohm Termination pad

    Contextual Info: PECL, LVDS, OCXO Page 1 - 7 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products Differential PECL Series Differential PECL Output, Some with Enable/ Disable Function Available in 9 Different Package/Configurations, See Next Pages


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