50-PIN LVDS Search Results

6-pin "454"

Contextual Info: CY2XF33 High-Performance LVDS Oscillator With Frequency Margining – Pin Control Features Functional Description • Low jitter crystal oscillator XO ■ Less than 1 ps typical RMS phase jitter ■ Differential LVDS output ■ Output frequency from 50 MHz to 690 MHz

Contextual Info: NB3L14S 2.5 V 1:4 LVDS Fanout Buffer The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. The NB3L14S LVDS signals will be buffered and replicated to identical LVDS copies of the Input

SN65LVDS049

Abstract: C101 DS90LV049 SN65LVDS049PW SN65LVDS049PWG4
Contextual Info: SN65LVDS049 5,0 mm x 6,4 mm www.ti.com SLLS575 – AUGUST 2003 DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS FEATURES • • • • • • • • • • • • • • DS90LV049 Compatible Up to 400 Mbps Signaling Rates Flow-Through Pin-out 50 ps Driver Channel-to-Channel Skew Typ

Contextual Info: SN65LVDS049 5,0 mm x 6,4 mm www.ti.com SLLS575 – AUGUST 2003 DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS FEATURES • • • • • • • • • • • • • • DS90LV049 Compatible Up to 400 Mbps Signaling Rates Flow-Through Pin-out 50 ps Driver Channel-to-Channel Skew Typ

Contextual Info: SN65LVDS049 5,0 mm x 6,4 mm www.ti.com SLLS575 – AUGUST 2003 DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS FEATURES • • • • • • • • • • • • • • DS90LV049 Compatible Up to 400 Mbps Signaling Rates Flow-Through Pin-out 50 ps Driver Channel-to-Channel Skew Typ

MC100EP16T

Abstract: MC10EP16T
Contextual Info: MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin

TC4-19

Abstract: SPC15354 CC0805K GRM188F51C224ZA01D C3216X5R1C106M LMH6554LE CC0805KRX7R7BB104 TNPW040249R9BEED SPC15182 TNPW040249R9BEE
Contextual Info: National Semiconductor Application Note 1945 Vannavong Philavanh June 29, 2010 General Description RL*4 , where RL is the impedance from pin 4 of the transformer to the load. For example, if RL = 50Ω for the test equipment, to achieve an impedance of 500Ω seen by the

ET5028-50

Abstract: et1310 switch SGMII
Contextual Info: Product Brief February 2006 ET5048-50 Single-Chip 48 x 1 Gbit/s Layer 2/3 Ethernet Switch Q Q Q Q Q Features Q Q Forty-eight 10/100/1000 Mbits/s Ethernet ports: — Forty-four-port, 6-pin SGMII interfaces to GbE copper PHYs — Four combo ports supporting either SGMII interface or

SFP EVALUATION BOARD 10G

Abstract: et-412
Contextual Info: Product Brief February 2006 ET5128-50 Single-Chip 28 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2/3 Ethernet Switch Q Q 1 Q Q Q Features Q Q Q Twenty-eight 10/100/1000 Mbits/s Ethernet ports: — Twenty-four-port, 6-pin SGMII interfaces to GbE copper PHYs — Four combo ports supporting either SGMII interface or

tpl 550

Abstract: 74AHC 74VHC ADCMP601 ADCMP604 ADCMP605 ADCMP605BCPZ jedec MO-203 ab
Contextual Info: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators ADCMP604/ADCMP605 Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage 1.6 ns propagation delay

Oscillator, 3.3Vdc PECL

Contextual Info: Model 635 LVPECL or LVDS CLOCK OSCILLATOR FEATURES • • • • • • • • • • • Standard 7.5x5.0mm Surface Mount Footprint Differential LVPECL or LVDS Output Fundamental or Overtone Crystal Low Phase Jitter Frequency Range 19.44 – 250 MHz

CY2DL818

Abstract: CY2DL818ZC CY2DL818ZCT CY2DL818ZI CY2DL818ZIT
Contextual Info: CY2DL818 1:8 Clock Fanout Buffer Features Low voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVDS Outputs Drives either a 50-ohm or 100-ohm load selectable Low input capacitance Low output skew Low propagation delay

Contextual Info: FEATURES Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage Propagation delay: 1.6 ns Power dissipation: 37 mW at 2.5 V Shutdown pin Single-pin control for programmable hysteresis and latch

1G07

Abstract: 74AHC 74VHC ADCMP601 CP123
Contextual Info: Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparator AD8465 Fully specified rail to rail at VCCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage Propagation delay: 1.6 ns Power dissipation: 37 mW at 2.5 V

Contextual Info: CY2DL818 1:8 Clock Fanout Buffer Features Low voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVDS Outputs Drives either a 50-ohm or 100-ohm load selectable Low input capacitance Low output skew Low propagation delay

Contextual Info: Model 658 CLOCK, HIGH FREQUENCY MULTIPLIER FEATURES • • • • • • • • • • Standard 7x5mm Surface Mount Footprint LVCMOS, Differential LVPECL or LVDS Outputs Frequency Range 38 – 750 MHz Frequency Stability, ±50 ppm Standard ± 25 ppm and ± 100 ppm available

Contextual Info: ADS6225, ADS6224 ADS6223, ADS6222 w w w .t i.c om SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007 DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE • FEATURES 1 • • • • • • • • • • Maximum Sample Rate: 125 MSPS

Contextual Info: PECL, LVDS, OCXO Page 1 - 7 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products Differential PECL Series Differential PECL Output, Some with Enable/ Disable Function Available in 9 Different Package/Configurations, See Next Pages

Contextual Info: Model 335 DIFFERENTIAL LVPECL AND LVDS VCXO FEATURES • • • • Standard 7x5mm Surface Mount Footprint Differential LVPECL or LVDS Outputs Frequency Range 19.44 – 212.50 MHz Frequency Stability, ±50 ppm Standard ± 25 ppm available • +2.5Vdc or +3.3Vdc Operation

Contextual Info: ADS5546 www.ti.com SLWS183D – NOVEMBER 2005 – REVISED APRIL 2007 14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • • • • • Maximum Sample Rate: 190 MSPS

Contextual Info: MAP, MAL, and MAV Series ¾ Industry Standard Package ¾ Wide Frequency Range ¾ RoHS Compliant Available ¾ Less than 1 pSec Jitter ELECTRICAL SPECIFICATION: LVDS LVPECL PECL 12.500MHz to 800.000MHZ See Part Number Guide for Options (See Part Number Guide for Options)

Contextual Info: CDCUN1208LP www.ti.com SCAS928 – MAY 2012 400 MHz Low Power 2:8 Fan-Out Buffer with Universal Inputs and Outputs Check for Samples: CDCUN1208LP FEATURES • 1 • • • • 2 Configuration Options via pins or SPI/I C : – Input Type (HCSL, LVDS, LVCMOS)

50 Ohm Termination pad

Contextual Info: PECL, LVDS, OCXO Page 1 - 7 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products LV7645D LVDS Series Low Voltage Differential Signal Output with Enable / Disable 80.00 MHz – 212.50 MHz

50 Ohm Termination pad

Contextual Info: PECL, LVDS, OCXO Page 1 - 7 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products Differential PECL Series Differential PECL Output, Some with Enable/ Disable Function Available in 9 Different Package/Configurations, See Next Pages