5-INPUT NAND GATES Search Results

Octal Latches open collector

Abstract: DM74ALS20A DM74ALS00A DM74ALS02 DM74ALS03B DM74ALS04B DM74ALS05A DM74ALS08 DM74ALS09 DM74ALS10A
Contextual Info: Logic Products by Family Bipolar-ALS Products Logic Product Function Product Description Package Voltage Node DM74ALS00A Gate Quad 2-Input NAND Gates DIP SOIC SOP 5 DM74ALS02 Gate Quad 2-Input NOR Gates DIP SOIC SOP 5 DM74ALS03B Gate Quad 2-Input NAND Gates with Open Collector Outputs

HEF4011BP

Abstract: hef4011
Contextual Info: HEF4011B gates QUADRUPLE 2-INPUT NAND GATE The HEF4011B provides the positive quadruple 2-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. JIUT?LJ^_iWLJoUilJT1 1 2 12 5 13 VqD ^8

Contextual Info: S G S-TH0I1S0N UYL !> | 7131237 0015131 8 I LOW POWER SCHOTTKY INTEGRATED CIRCUITS T74LS24 _ 67C D 15056 3 -/5 PRELIMINARY DATA QUAD 2-INPUT SCHMITT TRIGGER NAND GATE D ESC RIPTIO N The T54LS24/T74LS24 contains four 2-input NAND Gates which accept standard TTL input signals and

cmos nand gate open collector

Abstract: ttl nand gate 74LVQ00 TTL NOR Gate 74F00 series logic family nand gate NC7SZ332 cd4023bc TTL nand logic gate nand
Contextual Info: Logic Products by Function Gate Products Logic Product Family Product Description Package Voltage Node 74AC00 FACT Quad 2-Input NAND Gate DIP SOIC SOP TSSOP 3.3 5 74ACT00 FACT ACT Quad 2-Input NAND Gate DIP SOIC SOP TSSOP 5 74ACTQ00 FACT Quiet Series (ACTQ)

Contextual Info: GD54/74HC132, GD54/74HCT132 QUAD 2-INPUT SCHMITT-TRIGGER NAND GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 3 2 . They contain four independent 2-Input NAND gates. Each input has hysteresis and can, therefore, be used to enhance noise immunity

DM7413N

Contextual Info: co 5 p^. K&M National s Q co 5 in 2 o Sim Semiconductor DM5413/DM7413 Dual 4-Input NAND Gates with Schmitt Trigger Inputs General Description Absolute Maximum Ratings Note d This device con tains tw o independent gates each of w hich perform s the logic NAND fun ction. Each input

GD74HCT10

Abstract: GD74HC10
Contextual Info: GD54/74HC10, GD54/74HCT10 TRIPLE 3-INPUT NAND GATES General Description These devices are identical in pinout to the 5 4 /74 L S 1 0. They contain three independent 3-input NAND gates. These devices are characteriz­ ed for operation over wide temperature ranges to

cmos ic and gates datasheet

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD U74AHC00 CMOS IC QUADRUPLE 2-INPUT POSITIVE-NAND GATES „ DESCRIPTION The U74AHC00 is QUADRUPLE 2-INPUT POSITIVE-NAND GATES. Which provides the function Y=A*B . „ FEATURES * Operation voltage range: 2~5.5V * Max tPd of 6.5 ns at 5 V

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD U74AHC00 CMOS IC QUADRUPLE 2-INPUT POSITIVE-NAND GATES  DESCRIPTION The U74AHC00 is QUADRUPLE 2-INPUT POSITIVE-NAND GATES. Which provides the function Y = Α x Β .  FEATURES * Operation voltage range: 2~5.5V * Max tPd of 6.5 ns at 5 V

Contextual Info: IDT74LVC38A 3.3V CMOS QUAD 2-INPUT NAND GATE OPEN DRAIN EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC38A ADVANCE INFORMATION 3.3V CMOS QUAD 2-INPUT NAND GATE (OPEN DRAIN) WITH 5 VOLT TOLERANT I/O DESCRIPTION FEATURES: – – 0.5 MICRON CMOS Technology

SN74AS8003

Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

sot73

Abstract: HEF4012BPN HEF4012BP HEF4012BT HEF4012BD HEF4012B HEF4012BTD
Contextual Info: HEF4012B gates J DUAL 4-INPUT NAND GATE The HEF4012B provides the positive dual 4-input NAND function. The outputs are fu lly buffered for highest noise immunity and pattern insensitivity o f output impedance. J^Ui^UWUi^lJgLJTL V qd O j D 5 9 Oì Is I7 ¡6

HEF4011

Abstract: HEF4011BPN HEF4011BP SOT73 F4011B HEF4011B HEF4011BD Quadruple 2-input NAND gate DIL 14 M
Contextual Info: HEF4011B gates QUADRUPLE 2-INPUT NAND GATE The HE.F4011B provides the positive quadruple 2-input NAND function. The outputs are fu lly buffered fo r highest noise im m unity and pattern insensitivity of ou tput impedance. 1 2 11 12 5 13 Vq d Is I7 I2 D 6 u

GD74HC20

Abstract: GD74HCT20
Contextual Info: GD54/74HC20, GD54/74HCT20 DUAL 4-INPUT NAND GATES General Description These devices Pin Configuration are identical in pinout to the 5 4 /7 4 L S 2 0 . They contain two independent 4 -input NAND gates. These devices are characteriz­ ed for operation over wide temperature ranges to

SN74AS8003

Abstract: SN74AS8003PSR SN74AS8003PSRE4
Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

SN74AS8003

Abstract: SN74AS8003PSR SN74AS8003PSRE4 SN74AS8003PSRG4
Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

SN74AS8003

Abstract: SN74AS8003PSRE4 SN74AS8003PSRG4
Contextual Info: SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE TOP VIEW Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It

Contextual Info: o CM ÆM National Semiconductor 54F/74F20 Dual 4-Input NAND Gate General Description This device contains two independent gates, each of which performs the logic NAND function. Ordering Code: See Section 5 Logic Symbol Connection Diagrams IEEE/IEC Pin Assignment

hef4012bp

Contextual Info: HEF4012B gates DUAL 4-INPUT NAND GATE The HEF4012B provides the positive dual 4-input NAND function. The outputs are fu lly buffered fo r highest noise im m unity and pattern insensitivity o f ou tp u t impedance. fcl_l^J^UiT_r5U9T_m Vqd D o, o2 la I7 *6 I 5 n.c.

Contextual Info: h- co 33 ÆM National Semiconductor 54F/74F37 Quad Two-Input NAND Buffer General Description This device contains four independent gates, each of which performs the logic NAND function. Ordering Code: See Section 5 Connection Diagrams Logic Symbol Pin Assignment