4KX36 Search Results

Contextual Info: WTP4K36-XGX M/HITE /MICROELECTRONICS 4Kx36 Synchronous FIFO MODULE advanced* FEATURES • High S peed O p e ra tio n : 66.7, 40, 2 8 .6 M H z ■ 5 V ± 1 0% P o w e r S u p p ly ■ Packaging: ■ In d u s tria l and M ilit a r y T e m p e ra tu re Ranges

Contextual Info: a WTP4K36-XGX WHITE /MICROELECTRONICS 4Kx36 Synchronous FIFO MODULE advanced* FEATURES • ■ H igh S peed O p e ra tio n : 66.7, 40, 2 8 .6 M H z ■ 5 V + 1 0 % P o w e r S u p p ly Packaging: ■ In d u s tria l and M ilit a r y T e m p e ra tu re Ranges

723653

Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide

Contextual Info: PRELIMINARY CY7C43644V CY7C43664V/CY7C43684V 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features • 3.3V high-speed, low-power, bidirectional, first-in first-out FIFO mem ories w/ bus matching capabilities • 1 Kx36x2 (CY7C43644V)

fifo asi cypress

Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 PRELIMINARY CYPRESS 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Fully asynchronous and sim ultaneous read and write operation permitted Mailbox bypass register for each FIFO Parallel and Serial Programmable Almost-Full and

Contextual Info: PRELIMINARY CYPR] CY7C43643V CY7C43663V/CY7C43683V 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO w/ Bus Matching Fully asynchronous and sim ultaneous read and write operation permitted Mailbox bypass register for each FIFO Parallel and Serial Programmable Alm ost Full and Al­

723653

Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide

tdc 310

Abstract: ba6l BA6R 10 35L U1
Contextual Info: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

jtag cable lattice Schematic

Abstract: MC860 ORT82G5 ORT82G5-2BM680 the application of fpga in today hsi jtag cable
Contextual Info: FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP ORCA ORT82G5 Evaluation Board Evaluate 3.7Gbps SERDES + FPGA Quickly and Easily Making the Right Choice… Choosing the right device to drive 3.7Gbits/s data over your backplane can be a critical decision, but evaluating your options

CY7C43622

Abstract: CY7C43632 CY7C43642 CY7C43662 CY7C43682 7C43
Contextual Info: fax id: 5426 43632/ CY7C43622/43632/43642 CY7C43662/43682 ADVANCED INFORMATION 256/512/1K/4K/16K x 36 x 2 Bidirectional Synchronous FIFO Features • Low power — -Icc= 100 mA — Isb= 0.4 mA • Fully asynchronous and simultaneous read and write operation permitted

add round key for aes algorithm

Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

SECDED

Abstract: EP3SE50
Contextual Info: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640- in ROM mode only or 320-bit memory logic array blocks (MLABs),

crpa

Abstract: HD-SDI over sdh SSTL-15 HIV54001-1 SSTL-18 HC4GX35FF1517N M144K
Contextual Info: HardCopy IV Device Handbook, Volume 4 101 Innovation Drive San Jose, CA 95134 www.altera.com HC4_H5V4-1.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

CY7C436X4

Abstract: a935 CY7C43634 CY7C43644 CY7C43664 CY7C43684 B935
Contextual Info: CY7C43634 CY7C43664256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching 1CY7C43664 CY7C43644 CY7C43664 CY7C43684 1K/4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features • Fully asynchronous and simultaneous read and write

70V7519

Abstract: IDT70V7519 IDT70V7519S ba6l
Contextual Info: Š HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

hd-SDI driver

Abstract: HD-SDI over sdh PCI 1350 HIV54001-1 SSTL-15 SSTL-18 PRBS24
Contextual Info: Section I. HardCopy IV Device Datasheet This section provides the datasheet for the HardCopy IV device family. This section includes the following chapter: • Chapter 1, DC and Switching Characteristics of HardCopy IV Devices Revision History Refer to each chapter for its own specific revision history. For information on when

A179B

Abstract: B935 a1835 B-352 CY7C43643 CY7C43643V CY7C43663 CY7C43663V CY7C43683V CY7C436X3V
Contextual Info: V PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO w/ Bus Matching • Fully asynchronous and simultaneous read and write operation permitted • Mailbox bypass register for each FIFO • Parallel and Serial Programmable Almost-Full and Almost-Empty flags

A179B

Abstract: CY7C43644V CY7C43664V CY7C43684V CY7C436X4V
Contextual Info: V CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching • Fully asynchronous and simultaneous read and write operation permitted • Mailbox bypass register for each FIFO • Parallel and Serial Programmable Almost-Full and Almost-Empty flags

A179B

Abstract: a935 b935 CY7C43624 CY7C43634 CY7C43644 CY7C43664 CY7C43684
Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 PRELIMINARY 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching • Fully asynchronous and simultaneous read and write operation permitted • Mailbox bypass register for each FIFO • Parallel and Serial Programmable Almost-Full and Almost-Empty flags

723653

Abstract: 72V841 72825 72V3622 BI 7284 72V3613 723674 72V211 72V221 72V241
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’99/PC IDT FIFO Memory Products Width

SECDED

Abstract: sram 16k8 EP3SE50
Contextual Info: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.1 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640-bit memory logic array blocks

PLL 4046 4011 4017

Abstract: phase angle controller SIII52001-1 SSTL-15 SSTL-18
Contextual Info: Stratix III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V2-1.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Bidirectional 4K x 9 FIFO

Abstract: fifo pointer CY7C43624 CY7C43634 CY7C43644 CY7C43664 CY7C43684
Contextual Info: fax id: 5428 13, 624/43 CY7C43624/43634/43644 CY7C43664/43684 ADVANCED INFORMATION 256/512/1K/4K/16Kx36x2 Bidirectional Synchronous FIFO w/Bus Matching • Low power — Icc= 100 mA — Isb= 0.4 mA • Fully asynchronous and simultaneous read and write operation permitted

ddr3 sata controller

Abstract: OC48 SSTL-15 SSTL-18 DFE EQUALIZER ERROR SCRAMBLE
Contextual Info: Section I. Device Datasheet and Addendum for Stratix IV Devices This section includes the following chapters: • Chapter 1, DC and Switching Characteristics for Stratix IV Devices ■ Chapter 2, Addendum to the Stratix IV Device Handbook Revision History