4C4M4 Search Results

Contextual Info: V, M in n n N I m t 4C4M4Ai / b i 4 MEG X 4 DRAM 4 MEG x 4 DRAM DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single power supply: +5V *10% • Low power, 3mW standby; 200mW active, typical Al

j13000

Abstract: dram 4mx4 DD01B J1-30004-A LM 327 CN til 702 datasheet 4lc4m4e0 4c4m4 29SF
Contextual Info: H igh P erform an ce 4M x4 CMOS DRAM « II Features • Organization: 4,194,304 words x 4 bits • High speed A S4C 4M 4E0 A S4LC4M 4E0 4M X 4 CMOS EDO DRAM Advance information JEDEC standard package - 400 mil, 24/26-pin SOJ 5V power supply 4C4M4E0 3V power supply (4LC4M4E0)

Contextual Info: Advance information Features • O rganization: 4 ,1 9 4 ,3 0 4 w o rd s x 4 bits • H ig h speed - 50/6 0 ns RAS access time - 2 5/ 3 0 ns column address access time - 10/12 ns CAS access time • Low p o w er consum ption - Active: 908 mW max - Standby: S.S mW max, CMOS I/O

4C4M4EOQ-50JC

Abstract: 4C4M4EOQ-50TC 4C4M4EOQ-60JC 4C4M4EOQ-60TC AS4C4M4E1Q-50JC
Contextual Info: March 2001 4C4M4EOQ 4C4M4E1Q 4M ✕ 4 CMOS QuadCAS DRAM EDO family Features • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption

4lc4m4e0

Contextual Info: H i ” li P e r l o m i a i H r •■ \S4 4M 4H II AS4I C 4 M 4 I 0 Jl A 4M X4 CMOSDRAM t M x 4 C M O S I.IH) DRAM Advance information Features • TTL-compatible, three-state I/O • JEDEC standard package • Organization: 4,194,304 words x 4 bits • High speed

MT4C4M4

Contextual Info: PRELIMINARY 4C4M4B1 4 MEG X 4 DRAM MICRON I ItChNOLOCY INC. DRAM 4 MEG x 4 DRAM 5V, FAST PAGE MODE PIN ASSIGNMENT Top View • JEDEC- and industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5.0V ±10% power supply

4C4M4B1

Contextual Info: PRELIM INARY 4C4M4B1 4 MEG X 4 DRAM l^ iiC R n r s j DRAM 4 MEG x 4 DRAM 5V, FAST PAGE MODE PIN A SSIG N M E N T Top View • JEDEC- and industry-standard x4 pinout, timing, functions and packages • High-performance CM OS silicon-gate process • Single +5.0V ±10% pow er supply

4C4M4FOQ-50JC

Abstract: 4C4M4FOQ-50TC 4C4M4FOQ-60JC TSOP300
Contextual Info: March 2001 4C4M4FOQ 4C4M4F1Q 5V 4M X 4 CMOS QuadCAS DRAM fastpage mode Features • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption

on 707

Abstract: 4C4M4FOQ-50JC 4C4M4FOQ-50TC
Contextual Info: $GYDQFH#LQIRUPDWLRQ $67&707 24 $67&707)44 89#70#✕#7#&026#4XDG #7#&026#4XDG&$6 &$6#'5$0#+IDVWSDJH#PRGH, 89#70# #7#&026#4XDG &$6 #'5$0#+IDVWSDJH#PRGH, )HDWXUHV • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time

Contextual Info: H ig h P e r f o r m a n c e 4M X 4 CM OS DRAM » H A S4C 4M 4E0 A S4L C 4M 4E 0 4 M X 4 CMOS EDO DRAM Advance information Features • O r g a n iz a t io n : 4 , 1 9 4 , 3 0 4 w o r d s x 4 b its JED EC s ta n d a r d p a c k a g e • H ig h s p e e d - 4 0 0 m il, 2 4 /2 6 - p i n SOJ

4c4m4

Contextual Info: $GYDQFH#LQIRUPDWLRQ $67&707 24 $67&707(44 70#✕#7#&026#4XDG 70# #7#&026#4XDG&$6 #7#&026#4XDG&$6#'5$0#+('2,#IDPLO\ &$6#'5$0#+('2,#IDPLO\ HDWXUHV • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time

NEC D2732

Abstract: 41C1000 41256 81c4256 6264 SRAM 44256 dram NEC 2732 nec 4217400 814400 Texas Instruments eprom 2732
Contextual Info: New Page 1 DRAM ORGANIZATION/ DENSITY FUJISTU GOLDSTAR HITACHI HYNDAI MB GM HM HY 256K x 1 256K 81256 71C256 51256 MICRON MT 53C256 1256 MITSUBISHI M5M 4256 1M x 1(1M) 81C1000 71C1000 511000 531000 4C1024 41000 256K x 4(1M) 81C4256 71C4256 514256 534256 4C4256