40MBIT Search Results

UT8R1M39

Abstract: aeroflex sram edac UT8ER1M32
Contextual Info: FOR IMMEDIATE RELEASE: June 1, 2010 CONTACT: Teresa Farris MARCOM Manager Aeroflex Colorado Springs 719-594-8035 voice 719-594-8468 (fax) Email: teresa.farris@aeroflex.com www.aeroflex.com/Memories AEROFLEX ANNOUNCES PRODUCTION OF NEW 32 and 40Mbit SRAM

microread

Abstract: 64 QAM modulator demodulator HD49429F uncorrectable errors FEC soft 256qam HD49430F PQFP-100 equalizer algorithm multipath qam circuit CLK10M
Contextual Info: HD49430F Preliminary Specification Rev. 2 April 1, 1998 General Description HD49430F is a highly integrated Downstream Processor optimized for applications such as Cable Modems and Set-top boxes and forms a complete and optimal solution with its companion HD49429F Upstream

Contextual Info: GEC PLESSEY ISE MIC ONDUCT OR S | PRELIMINARY INFORMATION 2 1 2 1 - 1.0 SP9921 50 MBIT MANCHESTER BIPHASE DECODER The SP9921 is a bipolar m onolithic silicon integrated circuit for clock and data recovery from a M anchester biphase-m ark encoded signal It operates from a single 5V

Contextual Info: L64105 MPEG-2 Audio/Video Decoder LOGIC Preliminary Datasheet The L64105 is an integrated, low-cost source audio/video A/V decoder for use in MPEG-2 A/V decoding systems. The system block diagram in Figure 1 shows an application of the L64105 within an MPEG-2 system.

UT8R2M39

Abstract: UT8R4M39 UT8R1M39 DQ380 10206 UT8ER1M39 PWR50
Contextual Info: Standard Products UT8R1M39 40Megabit SRAM MCM UT8R2M39 80Megabit SRAM MCM UT8R4M39 160Megabit SRAM MCM Preliminary Data Sheet December 9, 2010 www.aeroflex.com/memories FEATURES ‰ 20ns Read, 10ns Write maximum access times available ‰ Functionally compatible with traditional 1M, 2M, or 4M x

LRS1816

Abstract: LRS1B03 LRS1B04 LRS1B06 LRS1B07 sharp page buffer
Contextual Info: NEW PRODUCT INFORMATION LRS1B03/04/06/07 4-chip Stacked CSP Combination Memory < Outline > A multitude of multimedia services, including the distribution of information, electronic settlements of accounts and even TV-phones, are predicted thanks to improved baud rates in next generation cellular phones.

Contextual Info: MITSUBISHI DIGITAL ASSP M66512P/FP LASER-DIODE DRIVER DESCRIPTION The M66512 is a semiconductor laser-diode driver for driving a specific type* of semiconductor laser, in which the anode of a semiconductor laser diode is connected in stem structure to the cathode of a monitoring photodiode.

tcam

Abstract: R8A20410BG renesas tcam tcam renesas renesas CAM R8A2041 Xelerated tcam TCAM chip Xelerated ternary content addressable memory
Contextual Info: 20Mbit QUAD-Search Content Addressable Memory Features & Benefits  20Mbit density Supports large routing tables and enables low-cost, low-power, more reliable system designs  360 Million Searches per Second MSPS per table Delivers the industry’s highest packet look-up

Contextual Info: CYF0018V CYF0036V CYF0072V 18/36/72-Mbit Programmable FIFOs 18/36/72-Mbit Programmable FIFOs Features Functional Description • Memory organization ❐ Industry’s largest first in first out FIFO memory densities: 18-Mbit, 36-Mbit, and 72-Mbit ❐ Selectable memory organization: x 9, × 12, × 16, × 18, × 20,

L64005

Abstract: L64005 A/V Decoder iso 13818-2 color on-screen display L64768 SBD15 pan drive to play in tv Audio video video audio mpeg buffer demultiplexer L64x08 Video-Decoder
Contextual Info: L64105 MPEG-2 Audio/Video Decoder Preliminary Datasheet The L64105 is an integrated, low-cost source audio/video A/V decoder for use in MPEG-2 A/V decoding systems. The system block diagram in Figure 1 shows an application of the L64105 within an MPEG-2 system.

ML44114N

Abstract: 20P2N-A n type laser diode driver current buffer ic 30mA laserdiode and Application Note, Data S laserdiode application mitsubishi laserdiode
Contextual Info: MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66512P/FP M66512P/FP LASER-DIODE DRIVER LASER-DIODE DRIVER FEATURES • Two kinds of outputs for monitoring laser power built in. comparator output and analog output • Pin provided for forced OFF of current circuit.

rold RCE

Abstract: 4288A
Contextual Info: MITSUBISHI DIGITAL ASSP M66512P/FP LASER-DIODE DRIVER DESCRIPTION The M66512 is a semiconductor laser-diode driver for driving a specific type' of semiconductor laser, in which the anode of a semiconductor laser diode is connected in stem structure to the cathode of a monitoring photodiode.

Contextual Info: CYF0018V CYF0036V CYF0072V 18/36/72-Mbit Programmable FIFOs 18/36/72-Mbit Programmable FIFOs Features Functional Description • Memory organization ❐ Industry’s largest first in first out FIFO memory densities: 18-Mbit, 36-Mbit, and 72-Mbit ❐ Selectable memory organization: x 9, × 12, × 16, × 18, × 20,

Contextual Info: CYF0018V CYF0036V CYF0072V 18/36/72-Mbit Programmable FIFOs 18/36/72-Mbit Programmable FIFOs Features Functional Description • Memory organization ❐ Industry’s largest first in first out FIFO memory densities: 18-Mbit, 36-Mbit, and 72-Mbit ❐ Selectable memory organization: x 9, × 12, × 16, × 18, × 20,

M66515FP

Abstract: laserdiode and Application Note, Data S n type laser diode driver m66515 20P2N-A PHOTODIODE PD laserdiode driver
Contextual Info: MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66515FP M66515FP LASER-DIODE DRIVER/CONTROLLER LASER-DIODE DRIVER/CONTROLLER PIN CONFIGURATION TOP VIEW OUTPUT TO SWITCHING CURRENT SETTING LOAD OUTPUT TO BIAS CURRENT SETTING LOAD BIAS CURRENT

Contextual Info: HD49430F Preliminary Specification HITACHI Rev. 2 April 1, 1998 General Description HD49430F is a highly integrated Downstream Processor optimized for applications such as Cable Modems and Set-top boxes and forms a complete and optimal solution with its companion HD49429F Upstream

Contextual Info: L64105ds 1 Fri Sep 5 17:06:27 1997 L64105 MPEG-2 Audio/Video Decoder LSI LOGIC P relim inary Datasheet The L64105 is an integrated, low-cost source audio/video A/V decoder for use in MPEG-2 A/V decoding systems. The system block diagram in Figure 1 shows an application of the L64105 within an MPEG-2 system.

Contextual Info: CYF2018V CYF2036V CYF2072V 18/36/72-Mbit Programmable Multi-Queue FIFOs 18/36/72-Mbit Programmable Multi-Queue FIFOs Features Functional Description • Memory organization ❐ Industry’s largest first in first out FIFO memory densities: 18-Mbit, 36-Mbit and 72-Mbit

ADSP21060

Abstract: ADSP21062 V200
Contextual Info: A R I E L C O R P O R AT I O N 2540 Route 130 Cranbury, NJ 08512 tel: 609-860-2900 fax: 609-860-1155 ariel@ ariel.com www.ariel.com ORDERING INFORMAT I O N HammerHead V200 Series: Ultra-high performance floating-point signal and array processing boards based on the

V.24 TO RS232 CABLE

Abstract: rs232 protocols rs232 protocol SP508 RS232/V.24 rs449 pinout RS423 RS449 RS-449 SP509
Contextual Info: APPLICATION NOTE ANI8 Solved by TM Sipex SP508 Multiprotocol Transceiver Introduction The serial port protocols used in telecom and data-com equipment often require multiple channels that operate using different electrical signals. Table 1 illustrates some serial port protocols and the signals required for each. For example, a

phase controller trigger ic

Abstract: automatic phase correction circuit diagram GC-IP200 3 phase analog controller sine wave gemac IP200 phase controller trigger Gemac IP200 TQFP64 PR-00026-50
Contextual Info: Interpolation Circuit GC-IP200 Features: The GC-IP200 interpolation IC has been designed for connection to incremental position and angular measurement systems with sine-shaped output signals with a 90° phase shift. It can be operated at a large number of transducer systems working

CYF0036V

Contextual Info: CYF0018V CYF0036V CYF0072V 18/36/72-Mbit Programmable FIFOs 18/36/72-Mbit Programmable FIFOs Features Functional Description • Memory organization ❐ Industry’s largest first in first out FIFO memory densities: 18-Mbit, 36-Mbit, and 72-Mbit ❐ Selectable memory organization: x 9, × 12, × 16, × 18, × 20,

Contextual Info: Standard Products UT8R1M39 40Megabit SRAM MCM UT8R2M39 80Megabit SRAM MCM UT8R4M39 160Megabit SRAM MCM Preliminary Data Sheet December 7, 2012 www.aeroflex.com/memories FEATURES  20ns Read, 10ns Write maximum access times available  Functionally compatible with traditional 1M, 2M, or 4M x

HD4942

Abstract: qam circuit
Contextual Info: HD49430F Preliminary Specification HITACHI Rev. 2 April 1, 1998 General Description HD49430F is a highly integrated Downstream Processor optimized for applications such as Cable Modems and Set-top boxes and forms a complete and optimal solution with its companion HD49429F Upstream