400SO Search Results

Contextual Info: 2 MEG x 8 EDO DRAM M IC R O N HRAM MT4LC2M8E7 MT4C2M8E7 U n M IV I FEATURES PIN ASSIGNMENT (Top View OPTIONS 28-Pin SOJ (DA-3) Vcc [ 1* DÛ1 [ 2. DQ2¿ 3 003 r 4 DQ4 5 WE# C 6 RAS# C 7 NCC 3 AIO L 9 A0 L 10 A1 C t t A2 12 A3 t 13 Vcc [ 14 MARKING • Voltages

Contextual Info: 1 MEG x 16 EDO DRAM |U|IC=RON MT4C1M16E5 MT4LC1M16E5 DRAM VrìfAlVl FEATURES • JEDEC- and industry-standard x l6 tim ing, functions, pinouts and packages • High-perform ance CM OS silicon-gate process • Single power supply +3.3V ±0.3V or 5V ±10%

MT4LC2M8E7

Contextual Info: 2 MEG x 8 EDO DRAM l^ lld R O N H P AM MT4LC2M8E7 MT4C2M8E7 U n M IV I FEATURES PIN ASSIGNMENT Top View OPTIONS 28-Pin SOJ (DA-3) 1• Vcc DQ1 c 2 DQ2C 3 □03 £ 4 DQ4C 5 WE# C 6 RAS# C 7 NCC 8 A 10L 9 A0 C 10 A l C 11 A2C 12 A3 13 Vcc 14 MARKING • Voltages

MT4LC1M16E5TG-6

Abstract: MT4C1M16E5 MT4LC1M16E5 1k 400
Contextual Info: 16Mb: 1 MEG x16 EDO DRAM EDO DRAM MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html FEATURES • JEDEC- and industry-standard x16 timing,

MT4C1M16E5

Abstract: MT4LC1M16E5 MT4LC1M16E5TG-6 0241K
Contextual Info: OBSOLETE 16Mb: 1 MEG x16 EDO DRAM EDO DRAM MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html FEATURES • JEDEC- and industry-standard x16 timing,

MT4C1M16E5

Abstract: MT4LC1M16E5 MT4LC1M16E5TG-6 X3554 1k 400
Contextual Info: 16Mb: 1 MEG x16 EDO DRAM EDO DRAM MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html FEATURES • JEDEC- and industry-standard x16 timing,

Contextual Info: 1 MEG x 16 EDO DRAM DRAM MT4LC1M16E5 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES • JEDEC- and industry-standard x l6 timing, functions, pinouts and packages • High-performance CMOS silicon-gate process

MT4C1M16E5

Abstract: MT4LC1M16E5 MT4LC1M16E5TGS
Contextual Info: 1 MEG x 16 EDO DRAM TECHNOLOGY, INC. MT4C1M16E5 MT4LC1M16E5 DRAM FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts and packages • High-performance CMOS silicon-gate process • Single power supply +3.3V ±0.3V or 5V ±10% • All inputs, outputs and clocks are TTL-compatible

Marking E5

Contextual Info: 1 MEG x 16 EDO DRAM DRAM MT4LC1M16E5 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • JEDEC- an d in d u stry -sta n d a rd x l6 tim ing, functions,

Contextual Info: 1 MEG x 16 EDO DRAM M IC R O N I TECHNOLOGY, INC. DRAM MT4LC1M16E5 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • JEDEC- an d in d u stry -sta n d a rd x l6 tim ing, functions,

marking 1PC 6-pin

Contextual Info: 1 MEG x 16 EDO DRAM MICRON I TECHNOLOGY. INC. DRAM MT4C1M16E5 MT4LC1M16E5 FEATURES • JEDEC- and industry-standard xl6 timing, functions, pinouts and packages • High-performance CMOS silicon-gate process • Single power supply +3.3V ±0.3V or 5V ±10%

Contextual Info: EDO DRAM TECHNOLOGY, INC. MT4LC2M8E7 DRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • Industry-standard x8 pinout, timing, functions and packages

Contextual Info: 1 MEG x 16 EDO DRAM DRAM M T4LC 1M 16E5 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Top View • JE D E C - a n d in d u stry -sta n d a rd x l 6 tim in g , fu n ctio n s,

Contextual Info: 1 M E G x 16 EDO DRAM V IIC Z R O N n P A V n * M M T4C 1M 16E 5 \ m M T4L C 1M 16E 5 FEATURES • JEDEC- and industry-standard x l6 tim ing, functions, pinouts and packages • High-perform ance CM OS silicon-gate process • Single pow er supply (+3.3V +0.3V or 5V ±10%

TT-612

Contextual Info: 1 MEG x 16 EDO DRAM MICRON I TECtWoLOBV. INC. DRAM M T4LC 1M 16E5 For the latest data sheet revisions, p/ease refer to the Micron Web site: www.micron.com/m ti/msp/htmi/da tasheet. h tmi FEATURES • JED EC- and industry-standard xl6 timing functions*, pinouts and packages

taa 723

Contextual Info: 2 MEG x 8 EDO DRAM TECHNOLOGY, INC. MT4LC2M8E7 MT4C2M8E7 DRAM FEATURES PIN ASSIGNMENT Top View • Industry-standard x8 pinout, timing, functions and packages • State-of-the-art, high-performance, low-power CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or +5V ±10%)