4 INPUTS OR GATE DATASHEET Search Results

AN3338

Abstract: STGIPL20K60 GIPL20K60 home inverter schematic diagram 4510 opamp
Contextual Info: STGIPL20K60 SLLIMM small low-loss intelligent molded module IPM, 3-phase inverter - 20 A, 600 V short-circuit rugged IGBT Datasheet − production data Features • IPM 20 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes

ATA6833

Contextual Info: Atmel ATA6833/ATA6834 BLDC Motor Driver and LIN System Basis Chip DATASHEET Features ● Atmel ATA6833 temperature range TJ = 150°C ● Atmel ATA6834 extended temperature range TJ = 200°C ● Direct driving of 6 external NMOS transistors with a maximum switching frequency

J2 Q24A B

Abstract: Q24A ICS98ULPA877A ICSSSTUAF32868B IDTCSPUA877A q9bq12b
Contextual Info: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs

5741

Abstract: 74VHC14
Contextual Info: 74VHC14 Hex Schmitt inverter Datasheet − production data Features • High speed – tPD = 5.5 ns typ. at VCC = 5 V ■ Low power dissipation – ICC = 2 A (max.) at TA = 25 °C ■ Typical hysteresis: Vh = 1 V at VCC = 4.5 V ■ Power-down protection on inputs

H4-16

Contextual Info: 74LCX125 Low-voltage CMOS quad bus buffer 3-state with 5 V tolerant inputs and outputs Datasheet − production data Features • 5 V tolerant inputs and outputs ■ High speed – tPD = 5.2 ns (max) at VCC = 3 V ■ Power-down protection on inputs and outputs

Contextual Info: FS7755-DS-10_EN Datasheet SEP 2009 F P r R ro SC ef pe ’ er rti en es ce O nl y REV. 1.0 FS7755 Fo Energy Metering IC with Impulse Output FS7755 Fo F P r R ro SC ef pe ’ er rti en es ce O nl y Fortune Semiconductor Corporation 富晶電子股份有限公司

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

IEC-CISPR25

Contextual Info: Atmel ATA6824C High Temperature H-bridge Motor Driver DATASHEET Features ● PWM and direction-controlled driving of four externally-powered NMOS transistors ● High temperature capability up to 200°C junction ● A programmable dead time is included to avoid peak currents within the H-bridge

Contextual Info: CENTELLAX MX1DS10P Datasheet 15 GHz Ultra - Variable Broadband Prescaler Features • • • • • • • Wide Operating Range: 0.05 - 15GHz Variable Divide Ratios: 2 to 220 Single-Ended and/or Differential Drive High Input Sensitivity Size: 6mm x 6mm

Contextual Info: CENTELLAX UXN6M9P Datasheet 9 GHz Divide-by-8 to 511 Programmable Integer Divider Features • • • • • • • Wide Operating Range: DC - 9 GHz Contiguous Divide Ratios: 8 to 511 Large Output Swings: >1 Vpp/side Single-Ended or Differential Drive Size: 6mm x 6mm

SMD DATASHEET

Contextual Info: UXN6M9P Datasheet 9 GHz Divide-by-8 to 511 Programmable Integer Divider Product Highlights • Wide Operating Range: DC-9 GHz 40 pin Quad Flat No Lead QFN 6x6 mm pkg, 0.5 mm pad pitch JEDEC MO-220 Compliant UXN6M9P XXXX Marking Information: UXN6M9P = Device Part Number

Contextual Info: 74LVC1G08 SINGLE 2 INPUT POSITIVE AND GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G08 is a single 2-input positive AND gate with a standard push-pull output. The device is designed for A 1 5 V CC A V CC operation with a power supply range of 1.65V to 5.5V. The

200 Amp bridge mosfet

Abstract: A3941 A3941KLPTR-T PWM Four quadrant control tr 4as AEC-Q100-002 IPC7351 JESD51-5 free RJP MOSFET
Contextual Info: A3941 Automotive Full Bridge MOSFET Driver Features and Benefits Description ▪ High current gate drive for N-channel MOSFET full bridge ▪ High-side or low-side PWM switching ▪ Charge pump for low supply voltage operation ▪ Top-off charge pump for 100% PWM

NC7SZ57

Contextual Info: Preliminary Revised February 2000 NC7SZ57 • NC7SZ58 TinyLogic UHS Universal Configurable 2-Input Logic Gates Preliminary General Description Features The NC7SZ57 and the NC7SZ58 are Universal Configurable 2-Input Logic Gates. Each device is capable of

A4989

Abstract: a3986 microstepping drive 42 resolutions Microstepping Control Dual Full-Bridge MOSFET Driver
Contextual Info: A3986 Dual Full-Bridge MOSFET Driver with Microstepping Translator Not for New Design These parts are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications.

Contextual Info: SN74LVC126A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCAS339H – MARCH 1994 – REVISED OCTOBER 1998 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V

JESD-78 1.8V

Abstract: 74LVC1G125W5 VM MARKING CODE SOT353
Contextual Info: 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments Top View ( Top View ) The 74LVC1G125 is a single non-inverting buffer/bus driver with a 3-state output. The output enters a high impedance state when a HIGH-level is applied to the output enable (OE)

NC7SZ57L6X

Abstract: 2 input XNOR GATE z58 diode NC7SZ57 NC7SZ57P6X NC7SZ58 NC7SZ58L6X NC7SZ58P6X SC70-6
Contextual Info: Revised May 2002 NC7SZ57 • NC7SZ58 TinyLogic UHS Universal Configurable 2-Input Logic Gates General Description Features The NC7SZ57 and the NC7SZ58 are Universal Configurable 2-Input Logic Gates. Each device is capable of being configured for 1 of 5 unique 2-input logic functions.

Contextual Info: FUJITSU MICROELECTRONICS 374=171=2 G D G 7 ci53 Q E3E D 'T - H i- Z b - O Z October 1989 Edition 1.0 FUJITSU DATASHEET- M B 8 1 C 6 8 A - 45-W CMOS 16K-BIT HIGH SPEED SRAM 4096 WORDS X 4 BITS SRAM WITH HIGH SPEED AND AUTOMATIC POWER DOWN The Fujitsu MB81C68A-W is 4096 words x 4 bits static random access memory fabricated

Contextual Info: June 1990 Edition 1.0 DATASHEET FUJITSU MB814400-80/-10/-12 CMOS 4,194,304 BIT FAST PAGE MODE DYNAMIC RAM CMOS 1,048,576 x 4 Bits Fast Page Mode Dynamic RAM The Fujitsu MB814400 is afully decoded CMOS Dynamic RAM DRAM that contains a total of 4,194,304 memory cells accessible in 4-bit increments. The MB814400

Contextual Info: SN74LVC1G98 CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES417H – DECEMBER 2002 – REVISED JUNE 2005 • FEATURES • • • • • • Available in the Texas Instruments NanoStar and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V

Contextual Info: SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE www.ti.com SCES503D – NOVEMBER 2003 – REVISED JUNE 2005 • • FEATURES • • • • • • • • Available in the Texas Instruments NanoStar and NanoFree™ Packages Low Static-Power Consumption ICC = 0.9 µA

IDT5T93GL061

Abstract: 5T93GL061
Contextual Info: IDT5T93GL061 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II DESCRIPTION: FEATURES: • • • • • • • • • • • IDT5T93GL061 The IDT5T93GL061 2.5V differential clock buffer is a user-selectable

SN74LVC1G57

Abstract: 65VCC
Contextual Info: SN74LVC1G57 SCES414M – NOVEMBER 2002 – REVISED OCTOBER 2011 www.ti.com CONFIGURABLE MULTIPLE-FUNCTION GATE Check for Samples: SN74LVC1G57 FEATURES 1 • 2 • • • • • • Available in the Texas Instruments NanoFree Package Supports 5-V VCC Operation