37256 Search Results

Contextual Info: 68+1 5Ç 7(670($685(0(17 3+$6(0$7&+(' $'$37256 &RPSOHWH VHWV RI DGDSWRUV 6HULHV 3& 7\SH  = ,WHP  ,QWHUIDFH  3& ,QWHUIDFH  *LYHQ E\ WKH DGDSWRU 0D[ IUHTXHQF\  *+] 3KDVH PDWFKLQJ ‘ ƒ #  *+] 6HW FRQVLVWV RI  3&3&  13&

37392

Abstract: 37185
Contextual Info: Features • Shields ESD sensitive items from charge and electrostatic discharges with lid in place . • Provides ESD and physical protection for ESD sensitive circuit boards. • Impregnated corrugated material; greater durability than coated or printed material.

CY37256P160-125AI

Abstract: CY37256P208-125NC CY37256P160-83AI
Contextual Info: fax id: 6148 PRELIMINARY 37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tS = 4.5 ns — tCO = 5.0 ns Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis

208-Lead

Abstract: CY37512 CY37512V CY37512VP208-66NI ultraISR CABLE
Contextual Info: PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37192

Abstract: CY37192V tlp 453
Contextual Info: PRELIMINARY CY37192 UltraLogic 192-Macrocell ISR™ CPLD Features • • • • • • • • • • • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • •

U208

Abstract: O15Z ol87 o1m 147 Y37512P208
Contextual Info: 3 r CYPRESS PRELIMINARY Ultra37512 UltraLogic 512-Macrocell ISR™ CPLD Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

U208

Abstract: CY37512 37256 CY37512V CY37512P208-100UMB u208 application note CY37512P208-83UMB CY37512P208-125NC
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ ^'Sf .-” ^ jjÉBT * ¿f5’00“’’*<'^1; .r7“T{• •■■■■■■ c PRELIMINARY CY37512 3, £,.* k v / k J UltraLogic 512-Macrocell ISR™ CPLD Simple Timing Model Features 512 macrocells in 32 logic blocks In-System Reprogrammable™ ISR™

K10P144M100SF2RM

Abstract: 30311 bosch bosch AL 1115 CV CHN 703 ua 761 BOSCH 0 261 230 235 Bosch AL 1130 CV bosch 30311 AD7B 1278r
Contextual Info: K10 Sub-Family Reference Manual Supports: MK10X128VLQ100, MK10X128VMD100, MK10X256VLQ100, MK10X256VMD100, MK10N512VLQ100, MK10N512VMD100 Document Number: K10P144M100SF2RM Rev. 3, 4 Nov 2010 K10 Sub-Family Reference Manual, Rev. 3, 4 Nov 2010 2 Freescale Semiconductor, Inc.

Bosch AL 1130 CV

Abstract: bosch AL 1115 CV bosch AL 1115 CV Battery Charger 30311 bosch K20P104M100SF2RM DIODE ga 30313 bosch ATC 1084 biosensor c programming hcs08
Contextual Info: K20 Sub-Family Reference Manual Supports: MK20N512VLL100, MK20N512VML100 Document Number: K20P104M100SF2RM Rev. 3, 4 Nov 2010 K20 Sub-Family Reference Manual, Rev. 3, 4 Nov 2010 2 Freescale Semiconductor, Inc. Contents Section Number Title Page Chapter 1 About This Document

CY3600

Contextual Info: fax id: 6149 SS i^K JS f r i s a l i i J F ; U FTV fST “ ¿ N &*• I F l m c b PRELIMINARY 37256V t i UltraLogic 256-Macrocell 3.3V ISR™ CPLD Features • Up to 192 1/Os — plus 5 d ed icated inp u ts including 4 clo ck inputs • 256 m a cro c ells in six te en logic blocks

K40P144M100SF2RM

Abstract: msc 1697 MK40X256 MK40X256VLQ100 100-Pin Package Pin-Out Diagram ARM JTAG cortex a9 MSC 1697 IC pin diagram lta 301 13.56 mhz human implant MK40X256VMD100
Contextual Info: K40 Sub-Family Reference Manual Supports: MK40X128VLQ100, MK40X128VMD100, MK40X256VLQ100, MK40X256VMD100, MK40N512VLQ100, MK40N512VMD100 Document Number: K40P144M100SF2RM Rev. 3, 4 Nov 2010 K40 Sub-Family Reference Manual, Rev. 3, 4 Nov 2010 2 Freescale Semiconductor, Inc.

CY37384

Abstract: CY37384V
Contextual Info: Back PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

CY37512

Abstract: CY37512V AE O47 CY37512P208-83UMB
Contextual Info: Back PRELIMINARY CY37512 UltraLogic 512-Macrocell ISR™ CPLD Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

5V19

Contextual Info: fax id: 6149 UltraLogic 256-Macrocell 3.3V ISR™ CPLD Up to 192 l/Os Feat u res — plus 5 dedicated inputs including 4 clock inputs • 256 macrocel l s in sixteen logic blocks Product - t erm clocking • I EEE standard 3.3V operation I EE E1149.1 JTAG boundary scan

TEA 1112 A

Abstract: TCS101
Contextual Info: Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Features — tco = 4 .5 ns • Product-term clocking • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes

Contextual Info: J S S f l ^ Y P R R S S PREL,mNARY CY37512V "5=" r'" UltraLogic 3.3V 512-Macrocell ISR™ CPLD Fully R o u tab le w ith 10 0% L og ic U tilization Features — JT A G -co m p liant o n -b o a rd p ro g ram m in g T he C Y 3 75 12V is desig ned w ith a robust routing arch itecture

R/37512/37512V

Contextual Info: W ARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — t PD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — ts = 8 ns — tco = 8 ns • Product-term clocking — JTAG-compliant on-board programming

Bosch CJ 840

Abstract: MK20DX256 freescale JTAG header 14 TPS bosch BOSCH 0 261 204 620 IC BOSCH ISO 9141
Contextual Info: K20 Sub-Family Reference Manual Supports: MK20DX256ZVLL10, MK20DN512ZVLL10 Document Number: K20P100M100SF2RM Rev. 6, Nov 2011 K20 Sub-Family Reference Manual, Rev. 6, Nov 2011 2 Freescale Semiconductor, Inc. Contents Section Number Title Page Chapter 1 About This Document

d478

Abstract: bootloader k40 49733 K10P100M100SF2RM LR 45212
Contextual Info: K10 Sub-Family Reference Manual Supports: MK10DN512ZVLL10 Document Number: K10P100M100SF2RM Rev. 5, 8 May 2011 K10 Sub-Family Reference Manual, Rev. 5, 8 May 2011 2 Freescale Semiconductor, Inc. Contents Section Number Title Page Chapter 1 About This Document

Contextual Info: PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

Contextual Info: . _ n « PRELIMINARY 37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

Contextual Info: . JMMT f | 37256V 1^,/ |-.-.y| J«$ UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7.0 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.0 ns • • • • •

Contextual Info: fax id: 6149 W CYPRESS 37256V PRELIMINARY UltraLogic TM 256-Macrocell 3.3V ISR CPLD • Up to 192 1/Os — plus 5 dedicated inputs including 4 clock inputs Features • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR