37256 Search Results

amphenol HE 301

Abstract: 1220H
Contextual Info: NOTES: MATERIALS BODY CONTACT THIRD AND - A. B. IMPEDANCE: DIELECTRIC VOLTAGE: CYCLES MARKING: BAG "AMPHENOL RF, 3 1-220H TO BE 1500 VRMS, MIN. STAMP IN "AMPHENOL" ECO APPR 7/3/90 37256 DR 45402 DR P R O - E / R D - D M I I 02 I 00 I R 3 / I6-Feb-1 I 48491

Contextual Info: 68+1 5Ç 7(670($685(0(17 3+$6(0$7&+(' $'$37256 &RPSOHWH VHWV RI DGDSWRUV 6HULHV 3& 7\SH  = ,WHP  ,QWHUIDFH  3& ,QWHUIDFH  *LYHQ E\ WKH DGDSWRU 0D[ IUHTXHQF\  *+] 3KDVH PDWFKLQJ ‘ ƒ #  *+] 6HW FRQVLVWV RI  3&3&  13&

cy37128

Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Contextual Info: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

CY37384

Abstract: CY37384V L0651
Contextual Info: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os

Contextual Info: • ■ J ^ m n r n n PRELIMINARY 37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM N K t t ♦ < ij / 5; PRELIMINARY *^ ' CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: PRELIMINARY Cr CY37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: Xgjf PRELIMINARY 37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

Contextual Info: fax id: 6149 W CYPRESS 37256V PRELIMINARY UltraLogic TM 256-Macrocell 3.3V ISR CPLD • Up to 192 1/Os — plus 5 dedicated inputs including 4 clock inputs Features • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR

T1119

Contextual Info: ^^W ^C Y P R K S S 37256V preliminary UltraLogic 3.3V 256-Macrocell ISR™ CPLD Features — t PD = 12 ns — ts = 7 ns • 256 m a cro c ells in sixteen log ic blocks — t co = 6.5 ns • 3.3 V In -S ystem R ep ro g ram m ab le™ IS R ™ • P ro d uct-term clo ckin g

Contextual Info: CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD Features — tpD = 12 ns — ts = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6 .5 ns • Product-term clocking — 3.3V ISR • IEEE 1149.1 JTAG boundary scan

O16I

Abstract: 7256P 99L0
Contextual Info: PREUM INAm 37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

Contextual Info: PREUM INAm Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

2832 eeprom

Abstract: Bosch CJ 840 IN 4002 MIC diode
Contextual Info: K20 Sub-Family Reference Manual Supports: MK20DX256ZVLL10, MK20DN512ZVLL10 Document Number: K20P100M100SF2RM Rev. 5, 8 May 2011 K20 Sub-Family Reference Manual, Rev. 5, 8 May 2011 2 Freescale Semiconductor, Inc. Contents Section Number Title Page Chapter 1

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37384

Abstract: CY37384V cpld internal
Contextual Info: Back PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •

37-25615

Abstract: CY37256 CY37256P160-125UMB
Contextual Info: UltraLogic 256-Macrocell ISR™ CPLD Features — tCo = 4 -5 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

CY37512

Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

1602 LCD

Abstract: MK30DN512ZV fd 1079 TEN 5-0522 49733 CHN 844 diode mk30DN512
Contextual Info: K30 Sub-Family Reference Manual Supports: MK30DX128ZVLQ10, MK30DX128ZVMD10, MK30DX256ZVLQ10, MK30DX256ZVMD10, MK30DN512ZVLQ10, MK30DN512ZVMD10 Document Number: K30P144M100SF2RM Rev. 5, 8 May 2011 K30 Sub-Family Reference Manual, Rev. 5, 8 May 2011 2 Freescale Semiconductor, Inc.

MK10DN512

Abstract: Freescale Kinetis MCUs HCS08 bootloader 49733 chn 437 PRN14
Contextual Info: K10 Sub-Family Reference Manual Supports: MK10DN512ZVMC10 Document Number: K10P121M100SF2RM Rev. 5, 8 May 2011 K10 Sub-Family Reference Manual, Rev. 5, 8 May 2011 2 Freescale Semiconductor, Inc. Contents Section Number Title Page Chapter 1 About This Document

adaa

Abstract: LC7470 176D DISPLAY DATA USING ROM CIRCUIT
Contextual Info: Ordering number: EN 3725 _ CMOS LSI No. 3725 I_ LC747Q Character and Pattern Display Control 1C Overview C haracter and pattern display control 1C fo r TV screen A character dot configuration is 12 x 18. The IC has 64 internat character ROMs and displays up to 288