370PS Search Results

Contextual Info: DS92LV090A DS92LV090A 9 Channel Bus LVDS Transceiver Literature Number: SNLS025C DS92LV090A 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from

PCIe cable pinout

Contextual Info: PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Features Description • 6 Differential Channel, 1 to 2 demux that will support 5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1 signals on the second path

ABT244

Abstract: CBT3244 CBT3383 SN74ABT244 SN74CBT16209 SN74CBT16214 SN74CBT16233 SN74CBT3244 SN74CBT6800 relais 5v 10ma
Contextual Info: EB 219 Crossbar Technology CBT Verfasser: Peter Forstner Datum: 18.07.95 Rev.: 1.0 Der vorliegende Bericht behandelt die Familie der CBT-Bausteine (Crossbar Technology). Nach der Vorstellung des inneren Aufbaus dieser Schaltungsfamilie werden DC- und AC-Eigenschaften vorgestellt. Den Abschluß bilden verschiedene Applikationsbeispiele die auf den besonderen Eigenschaften der

AN-808

Abstract: AN-971 AN-977 DS92LV090A DS92LV090ATVEH
Contextual Info: DS92LV090A 9 Channel Bus LVDS Transceiver General Description Features The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading,

AN1108

Abstract: AN-808 AN-903 AN918 DS92LV090 DS92LV090A DS92LV090ATVEH
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

ICS853052

Abstract: ICS853052AG ICS853052AGT MC100EP58 MO-187
Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS853052 DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS853052 is a Dual LVCMOS / LVTTL-toDifferential 2.5V, 3.3V, 5V LVPECL Multiplexer HiPerClockS

display 40 pin connector pinout

Contextual Info: PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Features Description • 6 Differential Channel, 1 to 2 demux that will support 5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1 signals on the second path

Application Note AN1108

Abstract: AN918 AN-903 DS92LV090 DS92LV090A DS92LV090ATVEH AN1108 AN-808 lvds 40 pinout AN-918
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

OD-S524-SC-MM

Abstract: OD-J6863-0A01 OD-S524-MU-MM cletop HA01 OD-J6863-HA01 OD-S524-FCPC-MM
Contextual Info: OE HYBRID 622.08Mbps Receiver OD-J6863-0A01/ HA01 OC-12: SR, IR-1, IR-2, LR-1, LR-2 and LR-3 STM-4: I-4, S-4.1, S-4.2, L-4.1, L-4.2 and L-4.3 1 Copyright C 1994-2001 NEC Corporation 11th September, 2001 Rev.8 - Contents 1. PRODUCT NUMBER . 3

1310p

Abstract: SY58609U SY58610U SY58611U
Contextual Info: SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to

1310p

Abstract: 609U SY58609U SY58609UMG SY58609UMGTR SY58610U SY58611U
Contextual Info: SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully differential CML 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 4.25Gbps.

Contextual Info: CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■

ICS853052

Abstract: ICS853052AG ICS853052AGLF ICS853052AGT MC100EP58 MO-187 circuit diagram of 32-1 multiplexer marking 52AL
Contextual Info: PRELIMINARY ICS853052 DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS853052 is a Dual LVCMOS / LVTTL-toICS Differential 2.5V, 3.3V, 5V LVPECL Multiplexer and HiPerClockS a member of the HiPerClocks™ family of High

3M Touch Systems

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

Contextual Info: CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth

Contextual Info: SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to

Contextual Info: SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully differential CML 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 4.25Gbps.

m68000 microprocessor users manual

Abstract: EC000 M68000 M68300 MC68000 MC68020 MC68EC000 bcd verilog 32-bit microprocessor architecture "Single-Port RAM"
Contextual Info: Order This Document by M68300/D MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION Custom 68300 Product Brief Custom 68300 Integrated Processors Motorola's Custom 68300 integrated processors allow the designers of high-volume digital systems to place their application-specific circuitry on chip with an M68000 family

Contextual Info: SY58610U 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to

Contextual Info: SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input General Description The SY58609U is a 2.5/3.3V, high-speed, fully differential CML 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 4.25Gbps.

Contextual Info: OBSOLETE DS92LV090AEP www.ti.com SNLS184B – JANUARY 2005 – REVISED APRIL 2013 DS92LV090AEP 9 Channel Bus LVDS Transceiver Check for Samples: DS92LV090AEP FEATURES DESCRIPTION • • • • • The DS92LV090AEP is one in a series of Bus LVDS transceivers designed specifically for the high speed,

85301AK

Abstract: ICS85301 ICS85301AK ICS85301AKT MO-220
Contextual Info: PRELIMINARY Integrated Circuit Systems, Inc. ICS85301 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85301 is a high performance 2:1 Differential-to-LVPECL Multiplexer and a member of the HiPerClockS HiPerClockS™ family of High Performance Clock

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth