36BITS Search Results

MB811

Abstract: TPC 8608
Contextual Info: November 1996 Revision 1.1 DATA SHEET FSA4UN364 2/4 -(60/70)J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. FSA4UN3644 supports 4K refresh. FSA4UN3642

Contextual Info: cP ÏITSIJ I A M. July 1997 Revision 1.0 data sheet FSA4UN364 2/4 B-60J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)B-60J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. FSA4UN3644B supports 4K refresh. FSA4UN3642B sup­

MB811

Contextual Info: July 1997 Revision 1.0 data sheet FSA4UN364 2/4 B-60J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)B-60J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. FSA4UN3644B supports 4K refresh. FSA4UN3642B supports 2K refresh.

pj 996

Abstract: Fujitsu IR c code
Contextual Info: <p Jun e l 996 Revision 1.0 HATA fíH F F T - FSA4UN364 2/4 -(60/70)J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. DM4M4N360 supports 4K refresh. DM4M2N360

MB811

Contextual Info: June1996 Revision 1.0 DATA SHEET FSA4UN364 2/4 -(60/70)J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. DM4M4N360 supports 4K refresh. DM4M2N360

MB8117400B-60PJ

Contextual Info: July 1997 Revision 1.0 data sheet FSA8UN3642B-60J G/S -S 32MByte (8M x 36) CMOS DRAM Module General Description The FSA8UN3642B-60J(G/S)-S is a high performance, 32-megabyte dynamic RAM module organized as 8M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package.

Contextual Info: November 1996 Revision 1.1 FUJITSU DATA SHEET FSA4UN364 2/4 -(60/70)J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. FSA4UN3644 supports 4K refresh. FSA4UN3642

MB811

Contextual Info: May1996 Revision 1.0 DATA SHEET DM4M 4/2 N360-(60/70)JG-IS 16MByte (4M x 36) CMOS DRAM Module General Description The DM4M(4/2)N360-(60/70)JG-IS is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. DM4M4N360 supports 4K refresh. DM4M2N360 supports

Contextual Info: cP IITSU July 1997 Revision 1.0 data sheet FSA8UN3642B-60J G/S -S 32MByte (8M x 36) CMOS DRAM Module General Description The FSA8UN3642B-60J(G/S)-S is a high performance, 32-megabyte dynamic RAM module organized as 8M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package.

Contextual Info: June1996 Revision 1.0 FUJITSU DATA S H E E T FSA4UN364 2/4 -(60/70)J(G/S)-S 16MByte (4M x 36) CMOS DRAM Module General Description The FSA4UN364(2/4)-(60/70)J(G/S)-S is a high performance, 16-megabyte dynamic RAM module organized as 4M words by 36bits, in a 72-pin, leadless, single-in-line memory module (SIMM) package. DM4M4N360 supports 4K refresh. DM4M2N360

5 PEN PC TECHNOLOGY apllications

Contextual Info: DATA SHEET PM PMC-970113 ISSUE 3 PMC-Sierra, Inc. PM3351 e l a n 1x100 SINGLE PORT FAST ETHERNET SWITCH PM3351 ELAN 1X100 SINGLE PORT FAST ETHERNET SWITCH DATA SHEET ISSUE 3: FEBRUARY 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

K7Q161852A

Abstract: K7Q161852A-FC10 K7Q161852A-FC13 K7Q161852A-FC16 K7Q163652A K7Q163652A-FC10 K7Q163652A-FC13 K7Q163652A-FC16
Contextual Info: K7Q163652A K7Q161852A 512Kx36 & 1Mx18 QDRTM b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. April, 30, 2001 Advance 0.1 1. Amendment 1 Page 3,4 PIN NAME DESCRIPTION W 4A) : from Read Control Pin to Write Control

10D-11

Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Contextual Info: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.

K7Q161864B-FC16

Abstract: D0-35 K7Q161864B K7Q163664B K7Q163664B-FC16
Contextual Info: K7Q163664B K7Q161864B 512Kx36 & 1Mx18 QDRTM b4 SRAM Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Jan. 27, 2004 Advance 1.0 1. Final spec release Mar. 18, 2004 Final Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: •$:»£ V HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3379S F ea tu re s: * * True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access - * * * * Com m ercial: 5/6ns max.

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: I l i l l l 1 IF V 1 F 1 1 U 1 ‘! S y P r • W 0 L HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3379S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access o f the same memory location ♦ High-speed clock to data access

Contextual Info: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

TC59LM836DKB

Abstract: TC59LM836DKB-33
Contextual Info: TC59LM836DKB-33,-40 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2 − 2,097,152-WORDS x 4 BANKS × 36-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network

CII51001-1

Abstract: CII51002-1 EP2C20 EP2C35 EP2C50 SSTL-18
Contextual Info: Section I. Cyclone II Device Family Data Sheet This section provides provides information for board layout designers to successfully layout their boards for Cyclone II devices. It contains the required PCB layout guidelines, device pin tables, and package

70v3319s133

Abstract: 70V3319 A12L IDT70V3319 IDT70V3319S 70V3319S 70V3319PRF
Contextual Info: HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3319S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

GE133

Abstract: cdva AT75C AT75C220 AT75C320 GT Plus Oncore "vector instructions" saturation FS Oncore
Contextual Info: Features • • • • • • • • • • • Fully Autonomous DSP System 16-bit Fixed-point OakDSPCore 24K x 16 of Uploadable Program RAM 16K x 16 of Data RAM 2K x 16 of X-RAM 2K x 16 of Y-RAM X-RAM and Y-RAM Accessible within the Same Cycle JTAG Interface Available on AT75C220 and AT75C320