33F50 Search Results

Contextual Info: EFasf Logic Programmable Pulse f ip n p r a tn r series UCIICI dIUI PPG-33F 3 Bit TTL Interfaced Features: • Precise pulse widths ■ 3-BIT address ■ 1 ns to 50 ns Incrmental steps ■ Trigger inherent delay Tdo = 3.5 ns ± Too = 5.0 ns ± ■ Inherent pulse width PW0 = 9 ns ± 2

PPG-33F-1

Abstract: PPG-33F-10 PPG-33F-15 PPG-33F-2 PPG-33F-20 PPG-33F-3 PPG-33F-40 PPG-33F-5 PPG-33F-50
Contextual Info: ïF ast Logic Programmable Pulse fip n p ra tn r s er ies : U G II G I d I U I ppg~33F 3 Bit T T L Interfaced Features: • Precise pulse widths ■ 3-BIT address ■ 1 ns to 50 ns incrmental steps ■ Trigger inherent delay T d o = 3.5 ns ± Too = 5.0 ns ±

33F2

Contextual Info: ïF a s t L o g i c d a ta V ^ y Programmable Puise fipnpratnr I I 6 II C I d IU I series ppg-33F 3 Bit TTLInterfaced d e la y W devices^ . Features: • Precise pulse widths ■ 3-BIT address ■ 1 ns to 50 ns incrmental steps ■ Triggerinherentdelay T do = 3.5 ns ± 2 ns