32LINE Search Results

ooby

Abstract: SBX1596-01 WD2412 betacam MA27 MA28 BD20 MA25 MA26 rd22
Contextual Info: S B X 1596-01 1/2 IL M _ 32LINE MEMORY FOR TBC — TO P V IEW — ( O W ' t r t M í - O O C O N Ü ^ ^ W M r - O O C O N ^ i n ^ í O C M t - O O ) nnnnnnnnnnnnnnnnnnnnnnnnnnnn "nïïïïnuïïïïiiïïïïïïuuïïnnuïïnnuïïuuuïïini i - M M ^ » n { D N C 0 0 ) O T - C y | « ^ i n ( 0 N 0 ) 0 ) O ' r W ( 0 5 f l 0 ( 0 N < 0

051b

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B - MARCH 1987 - REVISED JULY 1996 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems SN54F13 8 . . . J PACKAGE SN74F138. . . D OR N PACKAGE TOP VIEW u Incorporates Three Enable Inputs to

SN74F138

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051 A - D2932, MARCH 1987 - REVISED OCTOBER 1993 Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

042b

Contextual Info: 74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B - MAY 1988 - REVISED A P R IL I 996 D, N, OR PW PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Y1 [ 1 Y2 [ 2 Incorporates Three Enable Inputs to

Contextual Info: SN54LV138, SN74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC LS190P- FEBRUARY 19 9 3 - REVISED JULY 1996 EPIC Enhanced-Performance Implanted CMOS 2-fi Process Typical Vqlp (Output Ground Bounce) < 0.8 V at Vc c , Ta = 25°C SN54LV138. . . J OR W PACKAGE

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

sn74als138a ti

Abstract: SN54ALS138
Contextual Info: SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDAS055E – APRIL 1982 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify

Contextual Info: SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 D SN54HCT138 . . . J OR W PACKAGE SN74HCT138 . . . D, N, OR PW PACKAGE TOP VIEW A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC

Contextual Info: SN54LV138A, SN74LV138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS395C – APRIL 1998 – REVISED MAY 2000 D D D D D D description The ’LV138A devices are 3-line to 8-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation. SN54LV138A . . . J OR W PACKAGE

19ba

Contextual Info: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D3103. APRIL 1988 - REVISED APRIL 1993 * * * * * * * * Designed Specifically for High-Speed Memory Decoders and Data Transmission

SN74HC138D

Abstract: SN74HC138DR SN74HC138DT HC138 SN54HC138 SN74HC138 SN74HC138DBR SN74HC138N SN74HC138NSR SN54HC138J
Contextual Info: SN54HC138, SN74HC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Targeted Specifically for High-Speed D D D D D D D Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V

AC138

Abstract: AC138M CD54AC138 CD54AC138F3A CD74AC138 CD74AC138E CD74AC138M CD74AC138M96
Contextual Info: CD54AC138, CD74AC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS328A – JANUARY 2003 – REVISED FEBRUARY 2003 D D D D D D D D CD54AC138 . . . F PACKAGE CD74AC138 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

A115-A

Abstract: C101 SN74LV138AT
Contextual Info: SN74LV138AT 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER www.ti.com SCLS691 – AUGUST 2005 FEATURES • • Ioff Supports Partial-Power Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model A114-A

ic 4560

Abstract: IC 4560 CIRCUIT DIAGRAM S6B0719 4560 8 pin x6 voltage regulator 4560, 8 PINS pin diagram of 4560 ic COM103 COM82 RS 3213
Contextual Info: S6B0719 160 SEG / 105 COM DRIVER & CONTROLLER FOR STN LCD Sep. 2002. Ver. 0.8 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose,

Contextual Info: SN54LV138A, SN74LV138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS www.ti.com SCLS395L – APRIL 1998 – REVISED AUGUST 2005 FEATURES SN54LV138A . . . J OR W PACKAGE SN74LV138A . . . D, DB, DGV, NS OR PW PACKAGE TOP VIEW 2 16 15 3 14 4 13 5 12 6 11 7 10 8

Contextual Info: SN74LVC138A-EP 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER www.ti.com SCAS734B – NOVEMBER 2003 – REVISED JUNE 2005 • FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: SN54F138, SN74F138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SDFS051B – MARCH 1987 – REVISED JULY 1996 D D D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

Contextual Info: SN54HC138, SN74HC138 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D Targeted Specifically for High-Speed D D D D D D D Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range of 2 V to 6 V

CD74ACT238

Abstract: CD74ACT238E MS-001
Contextual Info: CD74ACT238 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCHS330 –FEBRUARY 2003 D D D D D D D D E PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Designed Specifically for High-Speed

SN74LV138

Abstract: SCLS190A
Contextual Info: SN74LV138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCLS190A - FEBRUARY 1993 - REVISED JULY 1995 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3-3 V, TA = 25°C Typical V o h v (Output V o h Undershoot)

AC138M

Abstract: AC138 CD54AC138 CD54AC138F3A CD74AC138 CD74AC138E CD74AC138M CD74AC138M96 CD74AC13
Contextual Info: CD54AC138, CD74AC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCHS328A – JANUARY 2003 – REVISED FEBRUARY 2003 D D D D D D D D CD54AC138 . . . F PACKAGE CD74AC138 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the

LC138

Abstract: A115-A C101 SN54LVC138A SN74LVC138A lc138a
Contextual Info: SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS www.ti.com SCAS291T – MARCH 1993 – REVISED JULY 2005 FEATURES • • • • • • Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.8 ns at 3.3 V Typical VOLP Output Ground Bounce

Contextual Info: SN54AHCT138, SN74AHCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS266L – DECEMBER 1995 – REVISED SEPTEMBER 2002 15 3 14 4 13 5 12 6 11 7 10 8 9 B C G2A G2B G1 Y7 16 B A NC VCC Y0 1 SN54AHCT138 . . . FK PACKAGE TOP VIEW C G2A NC G2B G1 15 Y0 14 Y1