32-BIT PARALLEL-IN SERIAL-OUT SHIFT REGISTER PROGRAM Search Results

MPEG 1 Audio Compression

Abstract: E0400 8 bit barrel shifter zoran zr
Contextual Info: ZfêRAN ZR38001 PROGRAMMABLE DIGITAL SIGNAL PROCESSOR PRELIMINARY FEATURES • High Performance Powerful Address Generation - ■ - 33 MIPs execution of multiple operation 32-bit instruction words - Single-cycle execution of three-data-operand instructions

digital clock using the Atmel AT89LP2052

Abstract: at89s52 Family with interfacing mic at89s52 micro controller at89c52 digital clock AT89LP2052 at89s2051 pwm AT89S52 AT89S52 data sheet atmel 1010 ELECTRONIC NOTICE BOARD USING AT89S52 circuit
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

ELECTRONIC NOTICE BOARD USING AT89S52 circuit

Abstract: at89s52 interrupt vector table Microcontroller AT89S52 Microcontroller AT89S52 block diagram at89s52 Family with interfacing mic CIRCUIT DIAGRAM FOR AT89S52 at89c52 base clock circuit diagram digital clock using at89s52 microcontroller AT89LP2052 AT89s52
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

WE-DSP16

Abstract: wedsp16
Contextual Info: Preliminary Data Sheet WE DSP16 Digital Signal Processor Description The WEDSP16 Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology. The standard DSP16 device described in this data sheet is packaged in an 84pin plastic leaded chip carrier. A military version

CIRCUIT DIAGRAM FOR AT89S52

Abstract: 25120p Microcontroller - AT89s52 at89s2051 pwm AT89LP2052 AT89S2051 AT89S52 MCS-51
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

Tuner sharp BPSK

Abstract: 16 bit parallel to serial NMT-900 HSP50214 HSP50214VC HSP50214VI HSP50210 polar modulator 3122 adj
Contextual Info: HSP50214 S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts

Tuner sharp QPSK

Abstract: 9031 code fir filter Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI
Contextual Info: February 2000 Programmable Downconverter Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be

AT89LP4052

Abstract: AT89S2051 AT89LP2052 AT89S52 MCS-51 LP4052 AT89C52 TIMER0
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

digital Serial FIR Filter

Abstract: NMT-900 Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI SAMPO
Contextual Info: HSP50214 S E M I C O N D U C T O R Programmable Downconverter June 1997 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts

bpsk modulator 20mhz

Abstract: dqpsk modulator CW25 DATASHEET SEMICONDUCTOR tag c3 625 800 HSP50210 HSP50214B HSP50214BVC HSP50214BVI 9031d
Contextual Info: HSP50214B TM Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter PDC performs down

HSP50210

Abstract: HSP50214B HSP50214BVI SAMPO intersil application note book CORDIC QAM modulation Tuner sharp QPSK
Contextual Info: HSP50214B TM Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous

Contextual Info: Advance Data Sheet WE DSP16A Digital Signal Processor Description The WE DSP16A Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology and is packaged in an 84pin plastic leaded chip carrier. The DSP16A

tuner 3402

Abstract: HSP50210 HSP50214B HSP50214BVC HSP50214BVI
Contextual Info: HSP50214B Semiconductor Data Sheet February 1999 File Number 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The

HSP50210

Abstract: HSP50214B HSP50214BVC HSP50214BVCZ HSP50214BVI HSP50214BVIZ E23LG 23BITS
Contextual Info: HSP50214B Data Sheet May 1, 2007 FN4450.4 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter PDC performs down

C 3197

Abstract: LATTICE plsi 3000 SERIES cpld C3198 equivalent c3198 C3207 isplsi1048c isp synario c3199 2032LV c3217
Contextual Info: ISP Architecture and Programming Subsection II — ISP Expert Introduction ispLSI Programming Details Boundary Scan ispLSI 3000 & 6000 Families ispGDS Programming Details ispGAL® Programming Details ISP Daisy Chain Details This section describes how to program Lattice Semiconductor Corporation’s (LSC) ISP™ devices once the

16C551

Abstract: fifo asynch asi
Contextual Info: WD16C451/WD16C551 INTRODUCTION 1.0 INTRODUCTION 1.1 DESCRIPTION 1 1.2 FEATURES Fully programmable serial interface charac­ teristics including: The low-power CMOS WD16C451AA/D16C551 is a single-device solution for serving one serial I/O port and one bidirectional parallel port on the IBM PC,

WEDSP16A

Abstract: WE-DSP16A
Contextual Info: £ a AT&T ^SESF Microelectronics Preliminary Data Sheet I//E DSP16A Digital Signal Processor Features Description • Pin- and instruction-compatible with the WE DSP16 Digital Signal Processor The WE DSP16A Digital Signal Processor is a 16-bit, high-speed, programmable integrated

32 line demux

Abstract: 74 demux SY87721L SY87724L SY87724LH1 SY87729L mpf-1
Contextual Info: 3.3V AnyRate MUX/DEMUX Up to 2.7GHz FEATURES SY87724L FINAL DESCRIPTION • Protocol transparent mux/demux operation up to 2.7GHz ■ Programmable to 4, 5, 8, or 10 bit parallel interfaces ■ Differential clock and serial inputs/outputs ■ Easily controlled by framer logic

Contextual Info: GC5018 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS169 – MAY 2005 Introduction 1.1 • • • • • FEATURES Four 16-Bit CMOS ADC Input Ports Programmable Closed Loop VGA Control With 6-Bit Outputs for Each ADC Input Port Provide Received Total Wide Band Power

SDXC

Abstract: SDXC controller 9706 src 12x12 bga thermal resistance B12 IC marking code c code for interpolation and decimation filter ic top 246 yn LG 631 IC F804 35023 ic
Contextual Info: HSP50216 Data Sheet August 17, 2007 Four-Channel Programmable Digital Downconverter FN4557.6 Features • Up to 70MSPS Input The HSP50216 Quad Programmable Digital Downconverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel

0X13

Abstract: GC5018 GC5018IZDL GC5316
Contextual Info: GC5018 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS169 – MAY 2005 Introduction 1.1 • • • • • FEATURES Four 16-Bit CMOS ADC Input Ports Programmable Closed Loop VGA Control With 6-Bit Outputs for Each ADC Input Port Provide Received Total Wide Band Power

structure interpolation CIC Filter

Abstract: SDXC F804 HSP50216 HSP50216KI HSP50216KIZ SD2C 00A140
Contextual Info: HSP50216 TM Data Sheet July 31, 2006 Four-Channel Programmable Digital DownConverter Features • Up to 70MSPS Input The HSP50216 Quad Programmable Digital DownConverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel

Contextual Info: 3.3V AnyRate MUX/DEMUX Up to 2.7GHz FEATURES PRELIMINARY SY87724L DESCRIPTION • Protocol transparent mux/demux operation up to 2.7GHz ■ Programmable to 4, 5, 8, or 10 bit parallel interfaces ■ Differential clock and serial inputs/outputs ■ Easily controlled by framer logic