32-BIT PARALLEL-IN SERIAL-OUT SHIFT REGISTER PROGRAM Search Results

MPEG 1 Audio Compression

Abstract: E0400 8 bit barrel shifter zoran zr
Contextual Info: ZfêRAN ZR38001 PROGRAMMABLE DIGITAL SIGNAL PROCESSOR PRELIMINARY FEATURES • High Performance Powerful Address Generation - ■ - 33 MIPs execution of multiple operation 32-bit instruction words - Single-cycle execution of three-data-operand instructions

Microcontroller

Abstract: AT89s52 AT89LP2052 AT89C52 INSTRUCTION SET at89s2051 pwm AT89S52 data sheet at89s52 interrupt vector table AT89S2051 MCS-51 Microcontroller - AT89s52
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

digital clock using the Atmel AT89LP2052

Abstract: at89s52 Family with interfacing mic at89s52 micro controller at89c52 digital clock AT89LP2052 at89s2051 pwm AT89S52 AT89S52 data sheet atmel 1010 ELECTRONIC NOTICE BOARD USING AT89S52 circuit
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

ELECTRONIC NOTICE BOARD USING AT89S52 circuit

Abstract: at89s52 interrupt vector table Microcontroller AT89S52 Microcontroller AT89S52 block diagram at89s52 Family with interfacing mic CIRCUIT DIAGRAM FOR AT89S52 at89c52 base clock circuit diagram digital clock using at89s52 microcontroller AT89LP2052 AT89s52
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

WE-DSP16

Abstract: wedsp16
Contextual Info: Preliminary Data Sheet WE DSP16 Digital Signal Processor Description The WEDSP16 Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology. The standard DSP16 device described in this data sheet is packaged in an 84pin plastic leaded chip carrier. A military version

CIRCUIT DIAGRAM FOR AT89S52

Abstract: 25120p Microcontroller - AT89s52 at89s2051 pwm AT89LP2052 AT89S2051 AT89S52 MCS-51
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

Tuner sharp BPSK

Abstract: 16 bit parallel to serial NMT-900 HSP50214 HSP50214VC HSP50214VI HSP50210 polar modulator 3122 adj
Contextual Info: HSP50214 S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts

Tuner sharp QPSK

Abstract: 9031 code fir filter Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI
Contextual Info: February 2000 Programmable Downconverter Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be

AT89LP4052

Abstract: AT89S2051 AT89LP2052 AT89S52 MCS-51 LP4052 AT89C52 TIMER0
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

at89lp4052-20su

Abstract: AT89LP2052
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

AT89S52

Abstract: AT89LP2052 at89s2051 pwm at89s52 pwm AT89S2051 MCS-51 PXM1
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

digital Serial FIR Filter

Abstract: NMT-900 Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI SAMPO
Contextual Info: HSP50214 S E M I C O N D U C T O R Programmable Downconverter June 1997 Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts

JB 2256

Abstract: atmel at89c52 architecture AT89LP2052
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.7V, 85°C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable ISP Flash Memory

HSP50210

Abstract: HSP50214B HSP50214BVC HSP50214BVI
Contextual Info: Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter PDC performs down

bpsk modulator 20mhz

Abstract: dqpsk modulator CW25 DATASHEET SEMICONDUCTOR tag c3 625 800 HSP50210 HSP50214B HSP50214BVC HSP50214BVI 9031d
Contextual Info: HSP50214B TM Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter PDC performs down

Contextual Info: HSP50214B Data Sheet File Number 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter PDC performs down

HSP50210

Abstract: HSP50214B HSP50214BVI SAMPO intersil application note book CORDIC QAM modulation Tuner sharp QPSK
Contextual Info: HSP50214B TM Data Sheet May 2000 File Number 4450.3 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous

16C552

Abstract: 16-BYTE 80MHZ IMP16C450 IMP16C552
Contextual Info: IMP16C552 Data Communications Dual Universal Asynchronous Receiver/Transmitter UART . with 16-BYTE FIFO & Parallel Printer Port Key Features Two fully programmable serial 1/0 channels (DC TO. 512K BAUD ) Fully prioritized independent interrupt system controls for each channel

Contextual Info: Advance Data Sheet WE DSP16A Digital Signal Processor Description The WE DSP16A Digital Signal Processor is a 16-bit high-speed programmable integrated circuit. The device is fabricated in low-power CMOS technology and is packaged in an 84pin plastic leaded chip carrier. The DSP16A

tuner 3402

Abstract: HSP50210 HSP50214B HSP50214BVC HSP50214BVI
Contextual Info: HSP50214B Semiconductor Data Sheet February 1999 File Number 4450.2 Programmable Downconverter Features The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The

IMP16C552

Abstract: marking code CJ6 sim 300 modem datasheet 16-BYTE 16C552 80MHZ IMP16C450 SLC-TS
Contextual Info: IMP16C552 Data Communications Dual Universal Asynchronous Receiver/Transmitter UART . with 16-BYTE FIFO & Parallel Printer Port Key Features Two fully programmable serial 1/0 channels (DC TO. 512K BAUD ) Fully prioritized independent interrupt system controls for each channel

bpsk modulator 20mhz

Abstract: Frequency Discriminator NMT-900 Numerically Controlled Oscillator tag c3 625 800 HSP50210 HSP50214A HSP50214AVC HSP50214AVI C 5021 F-R
Contextual Info: CT ODU ODUCT R P PR TE OLE UTE OBS UBSTIT 4B LE S SP5021 H SSIB December 1999 Programmable Downconverter PO Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK)

Contextual Info: HSP50214B S E M I C O N D U C T O R Programmable Downconverter February 1998 Features Description • Up to 65 MSPS Front-End Processing Rates CLKIN and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous • Processing Capable of >100dB SFDR