3090X Search Results

30021

Abstract: L48C L41C IC L44C DATASHEET L30C l31c L43C ORSO42G5 ORSO82G5 ORT42G5
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

AL437

Abstract: L97c L235C L103T L41C L140C L94C l165c L239C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

3090X

Abstract: 3070X
Contextual Info: Hazardous Location Industrial VRS Magnetic Speed Sensors DESCRIPTION Hazardous Location VRS sensors are designed for use in locations where explosion-proof or intrinsically safe sensors are required. The output signal of a VRS sensor is an ac voltage that varies

Architecture of TMS320C4X FLOATING POINT PROCESSOR

Abstract: dbam connector ppds TMS320C40 SPRU035 TMS320 TMS320C40
Contextual Info: TMS320C4x C Source Debugger User’s Guide 1992 Microprocessor Development Systems Printed in U.S.A., May 1992; reprinted August 1996 2547296–9761 revison A SPRU054 User’s Guide TMS320C4x C Source Debugger User’s Guide 1992 TMS320C4x C Source Debugger

L130C

Abstract: L74c l31c l97c l65c A311TC l146c l48c L202C L235C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

SPRU035

Abstract: TMS320 TMS320C40 SPRU054
Contextual Info: TMS320C4x C Source Debugger User’s Guide 1992 Microprocessor Development Systems Printed in U.S.A., May 1992; reprinted August 1996 2547296–9761 revison A SPRU054 User’s Guide TMS320C4x C Source Debugger User’s Guide 1992 TMS320C4x C Source Debugger

BAS 98 ATEX 3090x

Abstract: BAS98ATEX3090X BAS 98 ATEX 3090X 98 ATEX 3090x BAS98ATEX3089U GB-122 atex certificate GB-260 atex smc GB-220
Contextual Info: GB-distribution boxes and enclosures, polyester, to European Standards ATEX GB-distribution box and enclosures Description The GB-terminal box, both distribution box and empty enclosure, is manufactured of high impact resistance, glass-fibre reinforced polyester SMC & DMC providing extraordinary stability and corrosion

L62C

Abstract: 30021 3080e equivalent L41C Transistor BC 177 Datasheet 3080e l48c verilog code BIP-8 L71C l31c
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs July 2008 Data Sheet DS1028 Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

3080e equivalent

Contextual Info: ORCA ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSC April 2003 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted toward users needing high-speed backplane

Contextual Info: ORCA ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs January 2004 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s. This device is targeted toward users needing high-speed

L47C

Abstract: L146C L135 l54c L62C L97C verilog code of prbs pattern generator L71C L235C L43C
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC February 2005 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

Contextual Info: ORCA ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSC April 2003 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted toward users needing high-speed backplane

3013X

Abstract: EQUIVALENT BC 309 3093b
Contextual Info: ORCA ORSO82G5 1.0 - 2.7 Gbps SONET Backplane Interface FPSC October 2002 Preliminary Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO82G5 device. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO82G5 is a high-speed transceiver with an aggregate bandwidth of over 20 Gbits/s that is targeted towards users needing high-speed backplane interfaces for SONET and other non-SONET applications. The ORSO82G5 has 8 channels of integrated 1.02.7G SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable FPGA

484-pin BGA

Abstract: l37c 8 pin DS1028
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs November 2007 Data Sheet DS1028 Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

L41C

Abstract: l31c l44c IC L44C DATASHEET L30C L37C L43C l65c ORSO42G5 ORSO82G5
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs March 2004 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

Contextual Info: Hazardous Location Industrial VRS Magnetic Speed Sensors DESCRIPTION Hazardous Location VRS sensors are designed for use in locations where explosion-proof or intrinsically safe sensors are required. Passive VRS Variable Reluctance Speed Magnetic Speed sensors are simple, rugged devices that do not require an

30021

Abstract: L41C 3080c 3080e IC L44C DATASHEET l31c l39c ORSO42G5 ORSO82G5 ORT42G5
Contextual Info: ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2004 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSO42G5 and

L211C

Abstract: 3100B L17c R68T l71c
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC July 2004 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

L43C

Abstract: L130C l44c L239C l220c L235C L97c L62C L81C l31c
Contextual Info: ORCA ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC October 2007 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip SoC architecture, the ORSPI4 FPSC contains two

TI320C

Abstract: SPRU035 TMS320 TMS320C40
Contextual Info: TMS320C4x C Source Debugger User’s Guide 1992 Microprocessor Development Systems Printed in U.S.A., May 1992; reprinted August 1996 2547296–9761 revison A SPRU054 User’s Guide TMS320C4x C Source Debugger User’s Guide 1992 TMS320C4x C Source Debugger

TI320C40

Abstract: SPRU035 TMS320 TMS320C40
Contextual Info: TMS320C4x C Source Debugger User’s Guide 1992 Microprocessor Development Systems Printed in U.S.A., May 1992; reprinted August 1996 2547296–9761 revison A SPRU054 User’s Guide TMS320C4x C Source Debugger User’s Guide 1992 TMS320C4x C Source Debugger