3055192 Search Results

3055192 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY2308 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for	Original	CY2308 CY2308	PDF
Contextual Info: CY7C1370D CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ ■	Original	CY7C1370D CY7C1372D 18-Mbit 250-MHz	PDF
Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™	Original	CY7C1370D, CY7C1372D 18-Mbit CY7C1370D CY7C1372D	PDF
Contextual Info: RoboClock CY7B993V, CY7B994V High Speed Multi Phase PLL Clock Buffer Features Functional Description • 500 ps Max Total Timing Budget TTB window ■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation ■ Matched Pair Output Skew < 200 ps	Original	CY7B993V, CY7B994V CY7B993V CY7B994V	PDF
CY2308 Abstract: CY2308SI-4 Contextual Info: CY2308 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for	Original	CY2308 CY2308 CY2308SI-4	PDF
Contextual Info: CY7C1370D CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ ■	Original	CY7C1370D CY7C1372D 18-Mbit 250-MHz	PDF
Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Functional Description Features • Pin-compatible and functionally equivalent to ZBT™	Original	CY7C1370D, CY7C1372D 18-Mbit 250-MHz	PDF
Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and Functionally equivalent to ZBT™ ■ Supports 250-MHz Bus Operations with Zero Wait States ❐ Available speed grades are 250, 200, and 167 MHz	Original	CY7C1370D, CY7C1372D 18-Mbit 36/1M CY7C1370D CY7C1372D	PDF
Contextual Info: CY2308 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for	Original	CY2308 CY2308	PDF
Contextual Info: CY7B993V/CY7B994V RoboClock High Speed Multi Phase PLL Clock Buffer High Speed Multi Phase PLL Clock Buffer Features Functional Description • 500 ps Max Total Timing Budget TTB window ■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation	Original	CY7B993V/CY7B994V CY7B993V) CY7B994V) ps/1300	PDF
Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™	Original	CY7C1370D, CY7C1372D 18-Mbit 250-MHz	PDF
Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™	Original	CY7C1370D, CY7C1372D 18-Mbit CY7C1370D CY7C1372D	PDF
CY7C1370D Abstract: CY7C1372D Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™	Original	CY7C1370D, CY7C1372D 18-Mbit 250-MHz CY7C1370D CY7C1372D	PDF
Contextual Info: CY7C1370D, CY7C1372D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM with NoBL Architecture 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™	Original	CY7C1370D, CY7C1372D 18-Mbit CY7C1370D CY7C1372D	PDF

CY7B993V Abstract: CY7B993V-2AXC CY7B993V-2AXCT CY7B993V-2AXI CY7B994V Contextual Info: RoboClock CY7B993V, CY7B994V High Speed Multi Phase PLL Clock Buffer Features Functional Description • 500 ps Max Total Timing Budget TTB window ■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation ■ Matched Pair Output Skew < 200 ps	Original	CY7B993V, CY7B994V CY7B993V) CY7B994V) ps/1300 CY7B993V CY7B993V-2AXC CY7B993V-2AXCT CY7B993V-2AXI CY7B994V	PDF
cy2308sxi-2 Abstract: 3055192 CY2308SXI Contextual Info: CY2308 3.3 V Zero Delay Buffer 3.3 V Zero Delay Buffer Features The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for	Original	CY2308 CY2308 16-pin cy2308sxi-2 3055192 CY2308SXI	PDF
Contextual Info: RoboClock CY7B993V, CY7B994V High Speed Multi Phase PLL Clock Buffer Features Functional Description • 500 ps Max Total Timing Budget TTB window ■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation ■ Matched Pair Output Skew < 200 ps	Original	CY7B993V, CY7B994V CY7B993V CY7B994V	PDF