305313 Search Results

Contextual Info: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

CY7C1570KV18

Contextual Info: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

transistor SMD w26

Abstract: t2d 04 panasonic 74HC595 SMD AA7 smd diode smd diode u1j DIODE SMD b14 smd transistor ab2 SMD H24 smd diode af3 smd w20
Contextual Info: BGA Demo Board with FPGAs for SMII-to-MII Conversion Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document LXD9782 — BGA Demo Board with FPGAs for SMII-to-MII Conversion. Order Number: 249051-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

CY7C15632KV18

Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

Contextual Info: CY7C1480V25 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined Sync SRAM Functional Description[1] Features • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 167 MHz Registered inputs and outputs for pipelined operation

3M Touch Systems

Abstract: CY7C1570KV18
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-44701 Spec Title: CY7C1306CV25, 18-MBIT BURST OF 2 PIPELINED SRAM WITH QDR TM ARCHITECTURE (PRELIMINARY) Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE PRELIMINARY CY7C1306CV25 18-Mbit Burst of 2 Pipelined SRAM with

Contextual Info: CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

3M Touch Systems

Abstract: CY7C1570KV18
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

CY7C15632KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

CY7C1568KV18

Abstract: CY7C1570KV18 3M Touch Systems
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

CY7C15632KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

CY7C15632KV18

Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

305313

Contextual Info: PRELIMINARY CY7C1308DV25C 9 Mbit DDR I SRAM 4-Word Burst Architecture Functional Description Features n 9 Mbit Density 256 Kbit x 36 n 250 MHz Clock for High Bandwidth n 4-Word Burst to Reduce Address Bus Frequency n Double Data Rate (DDR) Interfaces (data transferred at 500 MHz at 250 MHz)

3M Touch Systems

Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations n 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-05282 Spec Title: �CY7C1480V25 72-MBIT 2M X 36/4M X 18/1M x 72 PIPELINED SYNC SRAM Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1480V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Functional Description[1]

CY7C15632KV18

Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Configurations Features • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

3M Touch Systems

Abstract: CY7C1570KV18
Contextual Info: CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-04310 Spec Title: CY7C1308DV25C, 9-MBIT DDR I SRAM 4WORD BURST ARCHITECTURE PRELIMINARY Sunset Owner: Jayasree Nayar Replaced By: NONE PRELIMINARY CY7C1308DV25C 9-Mbit DDR I SRAM 4-Word Burst Architecture Functional Description

CY7C15632KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

CY7C15632KV18

Contextual Info: CY7C15632KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features n Configurations Separate Independent Read and Write Data Ports p Supports concurrent transactions