3 BIT ERROR DETECTOR Search Results

d8253

Contextual Info: SN74AS632A 32 BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUIT D 3 3 9 7 , JAN U AR Y 1990 • Detects and Corrects Single-Bit Errors • Detects and Flags Dual-Bit Errors • Built-In Diagnostic Capability • Fast W rite and Read Cycle Processing Times

74LS631

Abstract: SN74LS630 DB2U
Contextual Info: TYPES SN54LS630, SN54LS631, SN74LS630, SN74LS631 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D 2550, MARCH 1980-REVISED APRIL 1985 TIM99630, TIM99631 Detects and Corrects Single-Bit Errors S N 5 4 L S 6 3 0 , S N 5 4 L S 6 3 1 . . . J D PACKAGE

MD15and

Abstract: SU16
Contextual Info: FUJITSU M I C R O E L E C T R O N I C S °il F U J IT S U D e | 3 7 ^ 7 1 ^ QOD4t.7S 3 | 16 BIT ERROR «CHECKING & CORRECTION T-^ S-i7 -MB1426 I _ 1 A p ril, 1986 E d itio n 1.0 DESCRIPTION The MB1426 Error Checking and Correction ECC device is designed to

Touch Screen Overlay

Abstract: gimbal micro-controller 1550 optical tranceiver connector
Contextual Info: PRELIMINARY specifications Tranceiver Characteristics Data rate Bit-error-rate BER Protocol Line-of-sight range Allowable atmospheric attenuation Typical availability1 2.5 Gbps full-duplex (100 kHz to 1.8 GHz 3-dB bandwidth) < 10 -9 independent / transparent

D4148

Abstract: 5033mp MSD4148 sod-123 marking code DV B7 MARKING DIAGRAM SOD-123 marking diagrams sod-123
Contextual Info: FAN5033 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller Features Description ƒ Selectable 2- or 3-phase operation at up to 1MHz per phase ƒ ±7.7mV worst-case differential sensing error over temperature ƒ ƒ Active current balancing between the output phases

Contextual Info: FAN5033 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller Features Description ̇ Selectable 2- or 3-phase operation at up to 1MHz per phase ̇ ±7.7mV worst-case differential sensing error over temperature ̇ ̇ Active current balancing between the output phases

D4148

Abstract: MSD4148 FAN5033 FAN5033MPX FAN5109 MLP-32 VR10 VR11 d879 A2 SOD-123
Contextual Info: FAN5033 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller Features Description ƒ Selectable 2- or 3-phase operation at up to 1MHz per phase ƒ ±7.7mV worst-case differential sensing error over temperature ƒ ƒ Active current balancing between the output phases

m13ab

Abstract: DT-23
Contextual Info: M 1 3 D e v ic e DS3/DS1 M U X / D E M U X TXC-03301 DATA SH EE T Preliminary FEATURES DESCRIPTION • Multiplexes/demultiplexes 28 DS1 signals into a DS3 signal. • M13 or C-bit parity mode operation • FEBE, C, or P-bit parity error insertion capability

TLC1549

Abstract: TLV1549 TLV1549C
Contextual Info: TLV1549C 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL SLAS071 A -J A N U A R Y 1 9 9 3 -R E V IS E D DECEMBER 1993 • Advanced LinEPIC Technology 3.3-V Supply Operation • 10-Bit-Resolution A/D Converter • Inherent Sample and Hold • Total Unadjusted Error. . . ±1 LSB Max

scrambler satellite v.35

Abstract: IESS-308 sCRAMBLER BUS13r iess-309 standard BPSK demodulator bpsk modulation and demodulation scrambler v.35 diagram intelsat scrambler IESS309
Contextual Info: PMC r PM7018 RPFEC ERROR CORRECTION CIRCUIT DATA SHEET FEATURES • Constraint length 7 convolutional encoder polynomials 133,171 • Vrterbi decoder with up to 3 bit soft decision inputs and an 80 stage trellis • Two versions for operation at the following information data rates:

Contextual Info: ANALOG DEVICES LC2M0S Complete, High Speed 12-Bit ADC AD7572A FEATURES Improved AD7572 Faster Conversion Time AD7572AXX03: 3 is AD7572AXX10: 10 jis 5 V and -1 2 V or -1 5 V Power Supply Operation Better Offset and Gain Error Specifications Extended Plastic Temperature Range

GR-253-CORE

Abstract: Si5023 STM-16
Contextual Info: Si5023 M ULTI -R ATE SONET/SDH CDR IC WITH L IMITING A MPLIFIER Features High-speed clock and data recovery device with integrated limiting amp: Supports OC-48/12/3, STM-16/4/ Bit error rate alarm 1, Gigabit Ethernet, and 2.7 Gbps Reference and referenceless

STM-16

Abstract: GR-253-CORE Si5023
Contextual Info: Si5023 M ULTI -R ATE SONET/SDH CDR IC WITH L IMITING A MPLIFIER Features High-speed clock and data recovery device with integrated limiting amp: Supports OC-48/12/3, STM-16/4/ Bit error rate alarm 1, Gigabit Ethernet, and 2.7 Gbps Reference and referenceless

GR-253-CORE

Abstract: Si5023 STM-16
Contextual Info: Si5023 M ULTI -R ATE SONET/SDH CDR IC WITH L IMITING A MPLIFIER Features High-speed clock and data recovery device with integrated limiting amp: Supports OC-48/12/3, STM-16/4/ Bit error rate alarm 1, Gigabit Ethernet, and 2.7 Gbps Reference and referenceless

dvd servo control ic DPD

Abstract: ic DPD 33P3720A Analog Front-End Error Detection analog servo circuit diagram dvd circuit diagram dvd servo control ic circuit diagram of DVD Rom 33P3720
Contextual Info: SSI 33P3720A DVD Analog Front-End with DPD, DPP and 3 Beam Error Detection Preproduction CHANNEL • 30 MHz bandwidth FEATURES GENERAL • Supports AGC and equalizer/filter up to DVD 3x speed and down to CD 1x speed • • Programmable attenuator min: -24 dB, 4-bit

Contextual Info: -OEC 2 0 1930 ANALOG ► D EV IC ES LC2M0S Complete, High Speed 12-Bit ADC PMAD7572A FEATURES Improved AD7572 Faster Conversion Time AD7572AXX03: 3 |xs AD7572AXX10: 10 jjls 5 V and - 1 2 V or - 1 5 V Power Supply Operation Better Offset and Gain Error Specifications

dvd servo control ic DPD

Abstract: 33P3720A Detector "Detector IC" CD DVD 33p3720 Error Detection Analog Front-End SPORT SSI33P3720A dvd rom circuit diagram ic DPD
Contextual Info: SSI 33P3720A DVD Analog Front-End with DPD, DPP and 3 Beam Error Detection Preproduction CHANNEL • 30 MHz bandwidth FEATURES GENERAL • Supports AGC and equalizer/filter up to DVD 3x speed and down to CD 1x speed • • Programmable attenuator min: -24 dB, 4-bit

6110-4

Abstract: AD7572 AD7572A AD7572AJN03 AD7572ALN03 MAX162ACNG MAX162BCNG PMAD7572AJN03 PMAD7572ALN03 ad7572ar10
Contextual Info: -OEC 2 a i93° ► ANALOG DEVICES LC2M0S Complete, High Speed 1 2-Bit ADC mmm FEATURES Improved AD7572 Faster Conversion Time A D 7572A XX 03: 3 |xs AD7572AXX10: 10 jxs 5 V and —12 V or —15 V Power Supply Operation Better Offset and Gain Error Specifications

Contextual Info: National Semiconductor 54F/74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

Contextual Info: & National Semiconductor 74F401 CRC Generator/Checker General Description Features The 'F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

Contextual Info: tß Semiconductor National 74F401 CRC Generator/Checker General Description Features The ’F401 Cycle Redundancy Check CRC Generator/ Checker provides an advanced tool for Implementing the most widely used error detection scheme In serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials in­

Biphase decoder

Abstract: BUS-1555 manchester Manchester block diagram BUS-63105 BUS-8559
Contextual Info: I L C DATA DEVICE CORP 32E ]> • Mt?07bR D0073b3 3 « D D C - f ~75^<77 C O R P O R A T IO N BUS-1555 MIL-STD-1553 MANCHESTER II DECODER FOR TEST EQUIPMENT FEA TU R ES • 16 MHz C LO C K R A T E DESCRIPTION AND APPLICATIONS Providing enhanced bit error capability

Contextual Info: NJU7512VT 1200 bps MSK Modem for Data Communication GENERAL DESCRIPTION PACKAGE OUTLINE The NJU7512 is a 1200bps MSK Minimum Shift Keying modem IC, which operates from 1.8V power supply. It includes 14.7456MHz oscillator and selectable OSC buffer for an external output, and a frame detector for receiving.

Contextual Info: Bit Error Rate Tester BERTScope BSA Series Datasheet Jitter Tolerance Compliance Template Testing with Margin Testing Fast Input Rise Time / High Input Bandwidth Error Detector for Accurate Signal Integrity Analysis Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour,