2A DB3 Search Results

M12L2561616A-6TIG2A

Contextual Info: ESMT M12L2561616A 2A Operation Temperature Condition -40°C~85°C SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES          ORDERING INFORMATION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation

Contextual Info: ESM T M13S5121632A 2A DDR SDRAM 8M x 16 Bit x 4 Banks Double Data Rate SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK )

Contextual Info: ESM T M12L2561616A 2A Operation Temperature Condition -40 C~85 C SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION FEATURES          JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation

Contextual Info: ESM T M13S2561616A 2A Operation Temperature Condition -40°C~85°C DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )

Contextual Info: ESM T M12L2561616A 2A SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION FEATURES „ „ „ „ „ „ „ „ „ „ JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

SDRAM

Abstract: M12L2561616A-5T 54-lead M12L2561616A
Contextual Info: ESMT M12L2561616A 2A Automotive Grade SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y GENERAL DESCRIPTION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs

DDR SDRAM

Contextual Info: ESMT M13S2561616A 2A Operation Temperature Condition -40°C~85°C DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK )

Contextual Info: ESM T M13S2561616A 2A DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

M12L2561616A-5TG2A

Abstract: M12L2561616A-7TG2A M12L2561616A-6TG2A
Contextual Info: ESMT M12L2561616A 2A SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y y y ORDERING INFORMATION JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 )

Contextual Info: ESM T M12L2561616A 2A Automotive Grade SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION „ „ „ „ The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits. Synchronous design allows precise cycle

Contextual Info: ESMT M13S2561616A 2A DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition

Contextual Info: 8 7 6 THE INFORMATION CONTAINED IN THIS DRAWING IS THE SOLE PROPERTY OF L-COM, INC. ANY REPRODUCTION IN PART OR WHOLE WITHOUT THE WRITTEN PERMISSION OF L-COM, INC. IS PROHIBITED. D 4 5 3 2 1 REVISIONS RoHS Compliant  4X 4-40 UNC-2A JACKSCREW DATE DESCRIPTION

Contextual Info: ESM T M13S2561616A 2A Automotive Grade DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition

Contextual Info: ESMT M13L2561616A 2A DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition

DDR SDRAM

Abstract: esmt m13s2561616a
Contextual Info: ESMT M13S2561616A 2A Automotive Grade DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition

Contextual Info: 8 7 4 5 6 3 2 REV E DESCRIPTION ECN 3779: DEFINED COLOR TO LIGHT GRAY, NEW FORMAT 4X, 4-40UNC-2A THUMBSCREW CHANGED BY D.FRISIELLO 2X, MOLDED PVC STRAIN RELIEF WITH 360° METAL FOIL SHIELD COLOR: LIGHT GRAY "J1" D "J2" UL STYLE 2464 37 CONDUCTOR CABLE PVC JACKET, COLOR: LIGHT GRAY

VMP4

Abstract: db3 c322 db3 c314 b30 c250 db3 c235 db3 c248 b30 c250 a2 db3 c244 b30 c300 - 1 FPS009-2405-0
Contextual Info: 8 D 7 6 5 4 2 1 D TP10 12V TO 14V DC INPUT R248 0R100 3V3 I limit = 0.1V / R . about 2.9A CR1 1V8 F1 STPS340U 3 J1 MP179_2.1mm 1 2 3 2A C256 2.2µF R257 0R100 TP11 + C18 470uF 25V TP17 U4 5 3V3 V+ 1 8 2 7 3 6 4 5 L3 22uH 3.8A + C22 220uF 16V 3 SHDN 2 3/5

b929

Abstract: DCD-725 d6849 A277D ad9a E7834
Contextual Info: 1234546789A BCDE4F6CA1ADA 2AAA8 A!"#A$%CA"&A A A 12324567829A4BCDBE37 F25D4297 "04A B4'%5A !FD7A 467E4.76A D.A 2A 52.9A 7A E7.9A .D682A 767E4.76A 779DCD84FA 576A .D682A 5D946D86A 492D829D78A 28FA F:82CDE.A

tba 450

Abstract: dc46a GUNN DIODE plessey
Contextual Info: GEC PLESSEY SENICONDS PACKAGED DETECTOR MODULES 43E D • 3?t.asaa oaisabi m ■ plsb 'X -o'i-o 'j DB3031 Germanium Backward Diode Detector Modules • • • • • • 0-1-18 GHz frequency range High sensitivity at zero bias High dynamic range > 4 5 d B

diac vbo 10V

Abstract: diac 5v vbo
Contextual Info: DB3, DB4 Bidirectional Si-Trigger-Diodes DIAC Bidirektionale Si-Trigger-Dioden (DIAC) Version 2004-10-01 Ø 1.9 Peak pulse current Max. Triggerimpuls 3.9 62.5 Breakover voltage Durchbruchsspannung Glass case Glasgehäuse Ø 0.52 Dimensions / Maße in mm

diac dB3

Abstract: db3 diac DIAC DB3 EQUIVALENT diac DB3 application note datasheet DIAC diac 5v SOD-27 DIAC DB4 DIAC diac 5v vbo
Contextual Info: DB3 . DB4 DB3 . DB4 Bidirectional Si-Trigger-Diodes DIAC Bidirektionale Si-Triggerdioden (DIAC) Version 2006-04-27 Breakover voltage Durchbruchspannung 3.9 Type 62.5 Ø 1.9 28 . 45 V Peak pulse current Max. Triggerimpuls ±2A Glass case Glas-Gehäuse

DB31

Abstract: db3 diac diac 5v vbo DIAC DIAC DB3
Contextual Info: DB3 , DB4 , DB31 DB3 , DB4 , DB31 Bidirectional Si-Trigger-Diodes DIAC Bidirektionale Si-Triggerdioden (DIAC) Version 2012-06-12 Breakover voltage Durchbruchspannung 3.9 Type 62.5 Ø 1.9±0.07 28 . 45 V Peak pulse current Max. Triggerimpuls ±2A Glass case

Contextual Info: DB3 . DB4 DB3 . DB4 Bidirectional Si-Trigger-Diodes DIAC Bidirektionale Si-Triggerdioden (DIAC) Version 2006-04-27 Breakover voltage Durchbruchspannung 3.9 Type 62.5 Ø 1.9 28 . 45 V Peak pulse current Max. Triggerimpuls ±2A Glass case Glas-Gehäuse

SOD-27

Abstract: DB31 DB32 diac 5v vbo
Contextual Info: DB3 , DB4 , DB31 , DB32 DB3 , DB4 , DB31 , DB32 Bidirectional Si-Trigger-Diodes DIAC Bidirektionale Si-Triggerdioden (DIAC) Version 2012-07-03 Breakover voltage Durchbruchspannung ±0.4 3.9 Type 62.5 ±3 Ø 1.9 ±0.1 Ø max 0.5 28 . 45 V Peak pulse current