28978 Search Results
28978 Datasheets (1)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| 2897813 | Phoenix Contact | Uncategorized - Miscellaneous - INLINE INTEGRATED DALI POWER SUP | Original | 79.5KB |
28978 Price and Stock
Phoenix Contact 2897839Inline Analog input Analog inputs 2 3-wire Transmission speed in the local bus 500 kBit/s Degree of protection IP20 including Inline connector and labeling field |
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Phoenix Contact 1628978M17-8EP1N8A8004S |
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Phoenix Contact 2897813Communications Module; inputs; 19.2-30VDC; DIN Rail; Spring Terminal | Phoenix Contact 2897813 |
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Broadcom Limited 5962-8978503KPA- Rail/Tube (Alt: 5962-8978503KPA) |
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5962-8978503KPA | Tube | 5 |
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5962-8978503KPA | 63 Weeks | 1 |
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5962-8978503KPA | 3,132 |
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Broadcom Limited 5962-8978503KYC- Bulk (Alt: 5962-8978503KYC) |
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5962-8978503KYC | Bulk | 5 |
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5962-8978503KYC | 9,868 |
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28978 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: CYWUSB6935 WirelessUSB LR 2.4 GHz DSSS Radio SoC Features • Low standby current < 1 µA ■ 2.4-GHz radio transceiver ■ Integrated 30-bit Manufacturing ID ■ Operates in the unlicensed Industrial, Scientific, and Medical ISM band (2.4 GHz to 2.483 GHz) |
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cywusb693530-bit13-mhz | |
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Contextual Info: CYWUSB6934 CYWUSB6932 WirelessUSB LS 2.4 GHz DSSS Radio SoC Features • Low standby current < 1 µA ■ 2.4-GHz radio transceiver ■ Integrated 30-bit Manufacturing ID ■ Operates in the unlicensed Industrial, Scientific, and Medical ISM band (2.4 GHz to 2.483 GHz) |
Original |
cywusb6934cywusb693230-bit | |
3M Touch SystemsContextual Info: CY7C2161KV18, CY7C2176KV18 CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
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cy7c2161kv18cy7c2176kv18cy7c2163kv18cy7c2165kv18+2 | |
28978Contextual Info: THIS DRAWING CONTAINS INFORMATION PROPRIETARY TO POSITRONIC AND IT S SUBSIDIARIES. POSITRONIC BELIEVES THE DATA ON THIS DRAWING TO BE RELIABLE, SINCE THE TECHNICAL INFORMATION IS GIVEN FREE OF CHARGE, THE R EMPLOYS SUCH INFORMATION AT HIS OWN DISCRETION AND RISK. POSITRONIC A SSU M ES NO RESPONSIBILITY FOR |
OCR Scan |
3k637028978 | |
CY7C0430CV-133BGI
Abstract: CY7C0430CV f18-100 chip K3216
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Original |
cy7c0430cv133-mhz18-bit-wide25-micron+3 | |
phase shifter 435 MHz
Abstract: CYV15G0203TB CYV15G0203TB-BGXC CYV15G0204RB
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cyv15g0203tb1500-mbpsphase shifter 435 mhzcyv15g0203tb-bgxc+1 | |
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Contextual Info: CYWUSB6935 WirelessUSB LR 2.4 GHz DSSS Radio SoC WirelessUSB™ LR 2.4 GHz DSSS Radio SoC Features • 13-MHz input clock operation ■ Low standby current < 1 µA ■ Integrated 30-bit Manufacturing ID 2.4-GHz radio transceiver ■ Operates in the unlicensed Industrial, Scientific, and Medical |
Original |
cywusb693513-mhz30-bit48-pin | |
3M Touch SystemsContextual Info: CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
Original |
cy7c2163kv18cy7c2165kv1818-mbit550-mhz+1 | |
3M Touch SystemsContextual Info: CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
Original |
cy7c2163kv18cy7c2165kv1818-mbit550-mhz+1 | |
CY8C24123A24SXContextual Info: CY8C24123A CY8C24223A, CY8C24423A PSoC Programmable System-on-Chip 1. Features • ■ ■ ■ ■ Powerful Harvard-architecture processor ❐ M8C processor speeds to 24 MHz ❐ 8 x 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ 2.4 to 5.25 V operating voltage |
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cy8c24123acy8c24223acy8c24423a32-bit+2 | |
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Contextual Info: CY62127DV30 MoBL 1-Mbit 64 K x 16 Static RAM CY62127DV30 MoBL® 1-Mbit (64 K × 16) Static RAM Features • Temperature ranges ❐ Industrial: –40 °C to 85 °C ■ Very high speed: 55 ns ■ Wide voltage range: 2.2 V to 3.6 V ■ Pin compatible with CY62127BV |
Original |
cy62127dv30cy62127bv48-ball44-pin | |
ASD20
Abstract: CY8C24123A CY8C24223A CY8C24423A 3P15
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cy8c24123acy8c24223acy8c24423a32-bit+3 | |
CY8C24123A
Abstract: CY8C24223A CY8C24423A mini projects based on opamp
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cy8c24123acy8c24223acy8c24423a14-bit+2 | |
CY62127BV
Abstract: CY62127DV30 CY62127DV30L CY62127DV30LL
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cy62127dv30cy62127bv48-ball44-lead+2 | |
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sgm 8905
Abstract: 3302 81A ir 3302 81A alcan joint compound snapdragon AKO 546 687 burglar alarm system abstract walkie talkie circuit diagram ZENER DIODES DZ 8407 tea 1601 t
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\fr\fm\21ded1pfrm0221ded1sgm 8905+9 | |
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Contextual Info: CY62127DV30 MoBL 1-Mbit 64 K x 16 Static RAM 1-Mbit (64 K × 16) Static RAM Features applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The |
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cy62127dv30i/o15 | |
2270M18
Abstract: 28978 accelerometer endevco 2270M8 Endevco shaker 2270M8 endevco accelerometer model 72 30700 shakers CS130L
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Original |
2270m1840khz28978accelerometer endevco 2270m8+7 | |
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Contextual Info: CY7C2163KV18, CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
Original |
cy7c2163kv18cy7c2165kv1818-mbit550-mhz | |
LA 7840
Abstract: CLARE 851 A24 24 DC 400A AUTOMATIC CIRCUIT BARKER SM 5126 BP hamada offset c.p. clare c70 CP CLARE 851 as 2653 atlantic Avtek oasis
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Original |
pi7c71001-877-pericomla 7840clare 851 a24+8 | |
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Contextual Info: CY7C2163KV18/CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports |
Original |
cy7c2163kv18/cy7c2165kv1818-mbit550-mhzcy7c2165kv18 | |
CPU 414-3 Processor Module
Abstract: mux 4011 inputs cmos RL 66 EEPROM
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Original |
cy8c24123acy8c24223acy8c24423a32-bit+4 | |
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Contextual Info: CY62127DV30 MoBL 1-Mbit 64 K x 16 Static RAM zebraCY62127DV30 MoBL® 1-Mbit (64 K × 16) Static RAM Features applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The |
Original |
cy62127dv30zebracy62127dv30cy62127bv48-ball+1 | |
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Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-15577 Spec Title: CY22180 VERY LOW JITTER FIELD AND FACTORY PROGRAMMABLE CLOCK GENERATOR Sunset Owner: Kelly Maas KVM Replaced by: None CY22180 Very Low Jitter Field and Factory Programmable Clock Generator Features Benefits |
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cy22180 | |
POULSBO
Abstract: jtag PL-2303 G682L09TT12U bpm t105 PC81 Sharp AL005241008 THP48 IT8512 quanta UTS6680
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100/133mhz100mhz96mhz14mhz+16 | |