28-PIN QFP Search Results

Contextual Info: 80C196KB10/83C196KB10/80C196KB12/83C196KB12 PACKAGING The 80C196KB is available in a 68-pin PLCC package, an 80-pin QFP package and a 68-pin PGA package. Contact your local sales office to determine the exact ordering code for the part desired. Package Designators: N = 68-pin PLCC, S = 80-pin QFP and A = 68-pin PGA.

Contextual Info: HITACHI/ LOGIC/ÂRRÂYS/HEH SIE » 44^503 Ü Ü 1 7 7 3 1 Ô7D IHITS HN62418 Series-T-46-13- 1 5 8M 512K x 16-bit and (1M x 8-bit) Mask ROM • DESCRIPTION The Hitachi HN62418 Series is an 8-Megabit CMOS Mask Programmable Read Only Memory organized either as 524,288 x

Contextual Info: HOLTEK r r HT1330 3 1/2 Digit Timer + Watch Features • • • • • • • • • • • • • • A re al tim e w atch A 20-hour ad ju stab le ran ge settin g count­ down tim er 20-m inute count-up d isp lay cycle tim e 20 hours of count-up tim e m axim um

Contextual Info: A E M Ä N ] ! DMF©[^G!Mini K] in t e l 8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER Chip-select Unit — 6 Chip-select Pins — Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select — Programmable Wait States 0-15 for Each Chip Select

Contextual Info: 8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER 1.0 PRODUCT OVERVIEW The 8XC196NU is a member of Intel’s 16-bit MCS 96 microcontroller family. The device features 1 Mbyte of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch

HN62428P

Contextual Info: H I TA C H I / L O G I C / A R R A Y S / M E 11 SIE » • M M T b SO B D01 7 73 ñ IBS HN62428 Series- Preliminary - T - H 4 - IS M S ’ 8M 512K x 16-bit and (1M x 8-bit) Mask ROM ■ DESCRIPTION The Hitachi HN62428 Series is an 8-Megabit CMOS Mask

Contextual Info: l p 13« PIMMMGT [PIF3EWEW in te l. 80L188EA8 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • 3V Operation, Vcc = 2.7V-5.5V ■ Full Static Operation ■ True CMOS Inputs and Outputs Integrated Feature Set — Static 186 CPU Core — Power Save, Idle and Powerdown

Contextual Info: SC608 Power PC 603/604 Motherboard Clock Generator Approved Product PRODUCT FEA TURES FREQiJE N C Y TABLE in hhz • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Supports PPC603 and PPC604 Processors. 5 CPU clocks Up to 12 SDRAM clocks for 3 DIMMs. 8 PCI synchronous clocks.

Contextual Info: in te i 80L188EA-13, -8 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • 3V O p e ra tio n , V c c = 2 .7 V -5 .5 V ■ F u ll S ta tic O p e ra tio n ■ T ru e C M O S In p u ts a n d O u tp u ts ■ Integrated Feature Set — Static 186 CPU Core — Power Save, Idle and Powerdown

S-PBGA-N272

Abstract: 6713 SPRU266
Contextual Info: TMS320C6713, TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS186J − DECEMBER 2001 − REVISED FEBRUARY 2005 D Highest-Performance Floating-Point Digital D D D D D Signal Processors DSPs : C6713/C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word

ea8 diode

Abstract: 6713 SPRU266
Contextual Info: TMS320C6713, TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS SPRS186J − DECEMBER 2001 − REVISED FEBRUARY 2005 D Highest-Performance Floating-Point Digital D D D D D Signal Processors DSPs : C6713/C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word

Contextual Info: • ■ i n t e i r a p y T r [F ^E¥D1 I 80C188EA20, 16, 12 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR 80C188 Upgrade for Power Critical Applications Full Static Operation True CMOS Inputs and Outputs Integrated Feature Set — Static 186 CPU Core — Power Save, Idle and Powerdown

Contextual Info: SM320C32−EP DIGITAL SIGNAL PROCESSOR SGUS038 - AUGUST 2002 D Controlled Baseline D D D D D D D D D D D D D SMJ320C30 and SMJ320C31 Object Code - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -55 °C to 125°C Enhanced Diminishing Manufacturing

Contextual Info: in t e i M80C187 80-BIT NUMERIC PROCESSOR EXTENSION Military High Performance 80-Bit Internal Architecture Two to Three Times M8087 Performance at Equivalent Clock Speed Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic Upward Object-Code Compatible from

Contextual Info: intei 1.0 Networking Silicon — 82555 Introduction The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is an IEEE 802.3 physical layer specification for use over two pairs of Category 5 unshielded twisted

80C188XL20

Contextual Info: in te i 80C188XL20, 16, 12, 10 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • L o w P o w er, Full S tatic V ersio n o f the 80 C 1 88 ■ D ire ct A d d res sin g C a p a b ility to 1 M b yte M em o ry an d 64 K b y te I /O ■ O p e ra tio n M o d e s Include:

Contextual Info: INTEL CORP UP/PRPHLS böE D MflSL.175 D1313S2 T45 P B @ S ) y T P IR 1 ¥ C 1 W In te l 8XL196KD COMMERCIAL CHMOS MICROCONTROLLER 87L196KD— 32 Kbytes of On-Chip OTPROM 3.0V to 3.6V Operation 16 MHz Operation Dynamically Configurable 8-Bit or 16-Bit Buswidth

Contextual Info: p ^ e u <o t ra n in te l 80C186XL20,16, 12, 10 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of 80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187 — Compatible Mode

SI3016

Contextual Info: TMS320C54V90 EMBEDDED V.90 MODEM DSP SPRS165F − JULY 2001 − REVISED OCTOBER 2003 D Provides Two-Chip Modem Solution D Data Rates from 300 bps to 56 Kbps D Data Modulation Standards D V.90, V.34, V.32bis, V.32, V.22bis, V.22, V.23, V.21 and V.23 Reversible Minitel , Bell 212,

Contextual Info: P R E O W flM V ir r t e l 87C51/80C51BH/80C31BH CH M O S SINGLE-CHIP 8-BIT M ICR O CO N TR O LLER WITH 4 K B Y T E S INTERNAL PRO G RAM M EM ORY 87C51/80C51BH/80C31BH—3.5 to 12 MHz, Vcc = 5V ±20% 87C51-1/80C51BH-1/80C31BH-1—3.5 to 16 MHz, Vcc = 5V ± 20%

Contextual Info: SM320F2810-EP, SM320F2811-EP, SM320F2812-EP SM320C2810-EP, SM320C2811-EP, SM320C2812-EP Digital Signal Processors Data Manual Literature Number: SGUS051A March 2004 − Revised October 2004 This document contains information on products in more than one phase of

Contextual Info: in te i INTEL 82555 10/100 Mbps LAN PHYSICAL LAYER INTERFACE • Optimal integration for lower cost solution — Integrated 10/100 Mbps single chip solution. — MQFP100 pin package. — Complete 10/100 Mbps Media Independent Interface Mil compliance with MDI support.

transistor bl p81

Abstract: transistor bl p87
Contextual Info: [p[F3 [0> !J T [PIFSEVOE^ in y 83C196EA CHMOS 16-BIT MICROCONTROLLER Automotive 32 MHz operation Optional clock doubler 2 Mbytes of linear address space 1 Kbyte of register RAM 3 Kbytes of code RAM 8 Kbytes of ROM Register-to-register architecture Stack overflow/underflow monitor with

Intel 82593

Abstract: n82593 82593SX
Contextual Info: 82593 CSMA/CD CORE LAN CONTROLLER • Supports Industry Standard LANs — IEEE 10BASE5 Ethernet* — IEEE 10BASE2 (Cheapernet) — IEEE 10BASE-T (TPE) ■ Simple, High-Performance Control and Data Interface _ — Control and Status via RD, WR, and CS Lines