26SEP2005 Search Results

Contextual Info: CY54FCT573T, CY74FCT573T 8-BIT LATCHES WITH 3-STATE OUTPUTS SCCS068 – OCTOBER 2001 D D D D D D D D D D Function and Pinout Compatible With FCT and F Logic Reduced VOH Typically = 3.3 V Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for

SN-74LS153N

Abstract: SN74LS153N SN74LS153N texas
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 76011012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 7601101EA

Contextual Info: SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 D D D D D D SN54ABT823 . . . JT OR W PACKAGE SN74ABT823 . . . DB, DW, OR NT PACKAGE TOP VIEW OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND These 9-bit flip-flops feature 3-state outputs

D4013B

Abstract: cd4013be D4013
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS023D − Revised April 2005 The CD4013B types are supplied in 14-lead hermetic dual-in-line ceramic packages F3A suffix , 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),

Contextual Info: SN54ABT374, SN74ABT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS111D – FEBRUARY 1991 – REVISED JULY 1994 • • • • State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA

military radar 20 pages documentation

Contextual Info: SN74LVTH244AĆEP 3.3ĆV ABT OCTAL BUFFER/DRIVER WITH 3ĆSTATE OUTPUTS SCAS691C − APRIL 2003 − REVISED OCTOBER 2003 D Controlled Baseline D D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN54S134J ACTIVE CDIP J 16 SN74S134N OBSOLETE PDIP N 16 1 Lead/Ball Finish MSL Peak Temp (3) TBD Call TI

Contextual Info: SN74LVTH18502AĆEP, SN74LVTH182502AĆEP 3.3ĆV ABT SCAN TEST DEVICES WITH 18ĆBIT UNIVERSAL BUS TRANSCEIVERS SCAS744A − DECEMBER 2003 − REVISED JUNE 2004 D Controlled Baseline D D D D D D D D UBT  Universal Bus Transceiver − One Assembly/Test Site, One Fabrication

Contextual Info: SN74LV14AĆEP HEX SCHMITTĆTRIGGER INVERTER SCLS499A − MAY 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D Supports Mixed-Mode Voltage Operation on − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 105°C

Contextual Info: SN54LS280, SN54S280, SN74LS280, SN74S280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS SDLS152 – DECEMBER 1972 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN74AHC245-EP OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCLS487A – MAY 2003 – REVISED JUNE 2003 D D D D D D D D DW OR PW PACKAGE TOP VIEW Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C

Contextual Info: REG104 REG 104 REG 104 SBVS025G – SEPTEMBER 2001 – REVISED SEPTEMBER 2005 DMOS 1A Low-Dropout Regulator FEATURES DESCRIPTION ● NEW DMOS TOPOLOGY: Ultra Low Dropout Voltage: 230mV typ at 1A and 3.3V Output Output Capacitor NOT Required for Stability ● FAST TRANSIENT RESPONSE

Contextual Info: CY54FCT244T, CY74FCT244T 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCCS071 – OCTOBER 2001 D D D D D D D D OEA DA0 OB0 DA1 OB1 DA2 OB2 DA3 OB3 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OEB OA0 DB0 OA1 DB1 OA2 DB2 OA3 DB3 CY54FCT244T . . . L PACKAGE

military radar 20 pages documentation

Contextual Info: SN74LVC373AĆEP OCTAL TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCAS737B − NOVEMBER 2003 − REVISED MAY 2004 D Controlled Baseline D D D D D D D D D Typical VOLP Output Ground Bounce − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

SN74LS595N

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-86717012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-8671701EA

SN74LVTH543-EP

Contextual Info: SN74LVTH543ĆEP 3.3ĆV ABT OCTAL REGISTERED TRANSCEIVER WITH 3ĆSTATE OUTPUTS SCBS772 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LS151DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS151DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LS151DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS151DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &

ALS541

Abstract: SN54ALS240A SN54ALS541 SN74ALS240A SN74ALS540 SN74ALS540-1N SN74ALS540N SN74ALS541
Contextual Info: SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025D – APRIL 1982 – REVISED MARCH 2002 D D 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Data Flowthrough Pinout All Inputs on

Contextual Info: SN54LS253, SN54S253, SN74LS253, SN74S253 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SDLS147 – SEPTEMBER 1972 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Contextual Info: SN74LVT125-EP 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS www.ti.com SCBS796A – JANUARY 2004 – REVISED JUNE 2005 • FEATURES • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: SN74LVTH16374ĆEP 3.3ĆV ABT 16ĆBIT EDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH 3ĆSTATE OUTPUTS SCBS779A − NOVEMBER 2003 – OCTOBER 2004 D Controlled Baseline D D D D D D D D D D D D Flow-Through Architecture Optimizes PCB − One Assembly/Test Site, One Fabrication

SNJ54121J

Abstract: sn74121 5962-9755301QCA 5962-9755301QDA SN54121J SN74121D SN74121DE4 SN74121DR SN74121DRE4 SN74121N
Contextual Info: SDLS042A - MAY 1983 - REVISED MAY 2005 A PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type 5962-9755301QCA ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC 5962-9755301QDA ACTIVE CFP W 14 1 TBD Call TI

Contextual Info: SN74HCT244ĆEP OCTAL BUFFER AND LINE DRIVER WITH 3ĆSTATE OUTPUTS SCLS562 − JANUARY 2004 D Controlled Baseline D D D D D D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing