25APR03 Search Results

0709A

Abstract: 164TL5
Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC ALL RIGHTS RESERVED. DIST REVISIONS AD 00 LTR DATE OWN APVD 25APR03 TK MZ DESCRIPTION 0 G 3 C -0 1 9 7 -0 3 SPECIFICATIONS: D M A TE RI A LS : D MOVING

Contextual Info: T H IS DRAWING IS U N P U B LIS H E D . RELEASED FOR PUBLICATION A L L RIGHTS COPYRIGHT — ,- RESERVED. BY TYCO ELECTRONICS CORPORATION. LOC D IS T AD 00 REVISIONS LTR D E S C R IP TIO N 0 G 3C — 0 1 9 9 — 03 DATE OWN APVD 25APR03 TK MZ SPECIFICATIONS!

Contextual Info: J THIS DRAWINGIS UNPUBLISHED. RELEASEDTORPUBLICATION ÏD R EC O M M E N D E D P .C . BO ARD H O LE PATTERN RECOMMENDED SO CKET 144 I 25APR03 I TK I KW I SEE SHEET 1 S ID E P .C . BO AR D SOCKET PO SN. 160 H O LE PATTERN S ID E PO SN. 5555555555555555555555555555555555555555

Contextual Info: SN54LV574A, SN74LV574A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS412F – APRIL 1998 – REVISED SEPTEMBER 2002 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 1D 2D 3D 4D 5D 6D 7D 8D 20 19 1Q 18 2Q

Contextual Info: SN54LV20A, SN74LV20A DUAL 4-INPUT POSITIVE-NAND GATE SCES339B – SEPTEMBER 2000 – REVISED DECEMBER 2000 D D D D SN54LV20A . . . J OR W PACKAGE SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS092B – Revised July 2002 The CD4724B types are supplied in 16-lead hermetic dual-in-line ceramic packages D and F suffixes , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (NSR suffix), 16-lead thin shrink

Contextual Info: SN54LVC04A, SN74LVC04A HEX INVERTERS SCAS281M – JANUARY 1993 – REVISED SEPTEMBER 2002 SN54LVC04A . . . J OR W PACKAGE SN74LVC04A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2 13 3 12 4 5 6 7 11 10 9 8 VCC 6A 6Y 5A 5Y 4A 4Y 1Y 2A 2Y 3A 3Y 14 1Y 1A NC

TI 046

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS090A – Revised March 2002 The CD4572UB types are supplied in 16-lead dual-in-line ceramic packages D and F suffixes , 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (NSR suffix), and in chip form (H suffix).

Contextual Info: SN54LVC573A, SN74LVC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCAS300O – JANUARY 1993 – REVISED SEPTEMBER 2002 20 1 19 2 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 1D 2D 3D 4D 5D 6D 7D 8D 20 2 19 1Q 3 18 2Q

Contextual Info: SN54LV07A, SN74LV07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCES337E – MAY 2000 – REVISED NOVEMBER 2001 D D D D D SN54LV07A . . . J OR W PACKAGE SN74LV07A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

TEXAS HC221

Abstract: 74hc221 TTL IC 74HC221
Contextual Info: [ /Title CD74 HC221 , CD74 HCT22 1 /Subject (High Speed CMOS Logic Dual Monos table Multi- CD54/74HC221, CD74HCT221 Data sheet acquired from Harris Semiconductor SCHS166D November 1997 - Revised July 2002 High Speed CMOS Logic Dual Monostable Multivibrator with Reset

Contextual Info: SN54LV373A, SN74LV373A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS407G – APRIL 1998 – REVISED OCTOBER 2002 19 3 18 4 17 5 6 16 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1Q 1D 2D 2Q 3Q 3D 4D 4Q 20 1D 1Q OE VCC 8Q 1 SN54LV373A . . . FK PACKAGE

integrated circuit sn74hc164n diagram

Abstract: SN74HC164N
Contextual Info: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115C – DECEMBER 1982 – REVISED DECEMBER 2002 D D D D D D D D D SN54HC164 . . . J OR W PACKAGE SN74HC164 . . . D, N, NS, OR PW PACKAGE TOP VIEW Wide Operating Voltage Range of 2 V to 6 V

Contextual Info: [ /Title CD54 HC00, CD54 HCT00 , CD74 HC00, CD74 HCT00 /Sub- CD54HC00, CD54HCT00, CD74HC00, CD74HCT00 Data sheet acquired from Harris Semiconductor SCHS116A High Speed CMOS Logic Quad 2-Input NAND Gate January 1998 - Revised November 2002 Features Description

Contextual Info: SN74LVC1G3157 SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH SCES424 – JANUARY 2003 D D D D D D D D D DBV OR DCK PACKAGE TOP VIEW 1.65-V to 5.5-V VCC Operation Useful for Both Analog and Digital Applications Specified Break-Before-Make Switching Rail-to-Rail Signal Handling

Contextual Info: SN54HC20, SN74HC20 DUAL 4ĆINPUT POSITIVEĆNAND GATES SCLS086E – DECEMBER 1982 – REVISED NOVEMBER 2002 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up to 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC D Typical tpd = 11 ns D ±4-mA Output Drive at 5 V

HC4040

Abstract: HC4040 application note
Contextual Info: SN54HC4040, SN74HC4040 12ĆBIT ASYNCHRONOUS BINARY COUNTERS SCLS160C – DECEMBER 1982 – REVISED DECEMBER 2002 D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns

Contextual Info: SN54HC640, SN74HC640 OCTAL BUS TRANSCEIVERS WITH 3ĆSTATE OUTPUTS SCLS303C – JANUARY 1996 – REVISED DECEMBER 2002 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up D D D D To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC

Contextual Info: SN54LS399, SN74LS399 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE SDLS174 – OCTOBER 1976 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS405C – APRIL 1998 – REVISED NOVEMBER 2002 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK A B C D ENP 16 CLK CLR NC VCC RCO 1 15 RCO 14 QA 2 3 A B NC C D 13 QB 12 QC 4 5

CI 4066

Contextual Info: SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR SCLS122C – DECEMBER 1982 – REVISED DECEMBER 2002 D D D D D D D D D D SN54HC193 . . . J OR W PACKAGE SN74HC193 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) Wide Operating Voltage Range of 2 V to 6 V

HC192

Contextual Info: [ /Title CD74 HC192 , CD74 HC193 , CD74 HCT19 3 /Subject (High Speed CMOS Logic Preset- CD54/74HC192, CD54/74HC193, CD54/74HCT193 Data sheet acquired from Harris Semiconductor SCHS163D September 1997 - Revised December 2002 High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

ic 4514 applications

Abstract: 4514 decoder 4515 CMOS
Contextual Info: [ /Title CD74 HC451 4, CD74 HC451 5 /Subject (High Speed CMOS CD54HC4514, CD74HC4514, CD74HC4515 Semiconductor SCHS280A - November 1997 - Revised October 2000 High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches Features Description

Contextual Info: SN74LVC841A 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS307I – MARCH 1993 – REVISED AUGUST 2002 D D D D D D D D D Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.7 ns at 3.3 V Typical VOLP Output Ground Bounce