256K Search Results

27C020-12

Abstract: 27PC020-12 LS020 A1025 LS020B 2097152-BIT
Contextual Info: TMS27C020 2097152-BIT UV ERASABLE PROGRAMMABLE TMS27PC020 2097152-BIT PROGRAMMABLE READ-ONLY MEMORY SM LS020B - N O V E M B E R 1990 - REVISED JU N E 1995 • Organization . . . 256K x 8 J PACKAGE TOP VIEW • Single 5-V Power Supply • Operationally Compatible With Existing

character generater

Contextual Info: 4M BIT 256K W O RD x 16 B IT / 512K W O R D x 8BIT CM OS M ASK ROM DESCRIPTION The BYTE The The TC534200P/F is a 4,194,304 bits read only memory organized as 262,144 words by 16 bits when is logical high, and is organized as 524,288 words by 8 bits when BYTE is logical low.

tms jl 27C256-15

Abstract: tms jl 27c256-12 tms jl 27C256-10 TMS JL 27C256-20 TMS JE 27C256-15
Contextual Info: TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES _ SMLS25BH- SEPTEMBER 1964 - REVISED NOVEMSER 1997 Organization . . . 32768 by 8 Bits J PACKAGE TO P VIEW Single 5-V Power Supply Pin Compatible With Existing 256K MOS

Contextual Info: OJ bq4014/bq4014Y UNITRODE- 256Kx8 Nonvolatile SRAM Features > Data retention in the absence of power > Automatic write-protection dur­ ing power-up/power-down cycles >• Industry-standard 32-pin 256K x 8 pinout >• Conventional SEAM operation; unlimited write cycles

Contextual Info: TM4256FL8, TM4256GU8 262,144 BY 8 BIT DYNAMIC RAM MODULES OCTOBER 1985 —REVISED FEBRUARY 1988 2 6 2 ,1 4 4 x 8 Organization TOP VIEW Utilizes Eight 256K Dynamic RAMs in Plastic Chip Carrier vss DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 NC NC DQ6 W Long Refresh Period . . . 4 ms (25 6 Cycles)

UNITRODE

Contextual Info: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features ➤ Data retention in the absence of power ➤ Automatic write-protection during power-up/power-down cycles ➤ Industry-standard 32-pin 256K x 8 pinout ➤ Conventional SRAM operation; unlimited write cycles

Ba 33 bco

Contextual Info: Direct RDRAM RAMBUS TM 32/36-M bit 256K x16/18x8d ADVANCE INFORMATION O verview The R am bus Direct RDRAM is a general p u rp o se high-perform ance m em ory device suitable for use in a broad range of applications including com puter mem ory, graphics, video, an d any other application

7273B

Contextual Info: SSRAM 256K18 256K x 18 SSRAM PIN ASSIGNMENT Top View Synchronous Burst SRAM, Flow-Through 100-pin TQFP SA SA CE\ CE2 NC NC bwB\ BWa\ CE2\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA FEATURES VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC

Contextual Info: SSRAM 256K36 256K x 36 SSRAM PIN ASSIGNMENT Top View Flow-Through, Synchronous Burst SRAM 100-pin TQFP (DQ, DQC & DQCR) FEATURES              DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss

74ALS6302

Abstract: la 7184 74ALS6301 M 6302 XP 74als630
Contextual Info: SN74ALS6301, SN74ALS6302 DYNAMIC MEMORY CONTROLLERS D 2 9 0 0 . JA N U A R Y 1 9 8 6 —REVISED M A R C H 1 9 8 8 Provides Control for 16K, 64K. 256K, and 1M Dynamic RAMs SN 74ALS6301, S N 7 4A LS 6 30 2 . . Highest-Order Two-Address Bits Select One of Four Banks of RAMs

Contextual Info: Datasheet Serial EEPROM Series Standard EEPROM I2C BUS EEPROM 2-Wire BR24Gxxx-3A (128K 256K 1M) General Description BR24Gxxx-3A is a serial EEPROM of I2C BUS Interface Method Features Packages W(Typ) x D(Typ)x H(Max) „ All controls available by 2 ports of serial clock(SCL) and

Contextual Info: Advance Information CAT25C256 256K-Bit SPI Serial CMOS E2PROM FEATURES • 100,000 Program/Erase Cycles ■ 5 MHz SPI Compatible ■ 100 Year Data Retention ■ 1.8 to 6.0 Volt Operation ■ Self-Timed Write Cycle ■ Hardware and Software Protection ■ 8-Pin DIP/SOIC and 20-Pin TSSOP

rg5H20

Abstract: fm25h20-g FM25H20-DG FM25H20-GTR FM25H20G
Contextual Info: Pre-Production FM25H20 2Mb Serial 3V F-RAM Memory Features 2M bit Ferroelectric Nonvolatile RAM • Organized as 256K x 8 bits • High Endurance 100 Trillion 1014 Read/Writes • 10 Year Data Retention • NoDelay Writes • Advanced High-Reliability Ferroelectric Process

MS8104166

Abstract: MSM518222A PEDS8104166-01
Contextual Info: PEDS8104166-01 1Semiconductor MS8104166 This version: Dec. 2001 Preliminary Dual FIFO 262,214 Words x 8 Bits × 2 GENERAL DESCRIPTION The MS8104166 is a single-chip 4Mb FIFO functionally composed of two Oki’s 2Mb FIFO (First-In First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation.

10-15V

Abstract: X5563 X5563S8 X5563S8I
Contextual Info: Preliminary Information X5563 CPU Supervisor with 256Kbit SPI EEPROM FEATURES DESCRIPTION • Selectable watchdog time — 0.15s, 0.4s, 0.8s off • Low VCC detection and reset assertion —Four standard reset threshold voltages —Re-program low VCC reset threshold voltage

9l reset

Abstract: CY7C0852V-133AC CY7C09289V CY7C09369V CY7C09379V
Contextual Info: CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description

W27C020-70

Abstract: W27C020 W27C20-70 IN914 W27C020-12 W27C020-90 W27C020P-12 W27C020P-70 W27C020P-90
Contextual Info: Preliminary W27C020 256K x 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C020 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 8 bits that operates on a single 5 volt power supply. The W27C020

NS41256L15

Abstract: PDM41256V
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 11/28/95 Last Update Date: 02/05/97 Last Major Revision Date: 11/28/95 MNNS41256L15-X REV 0A0 256K Static RAM 32K x 8 bit General Description NS41256L15 is a high performance, low power version CMOS static RAM organized as 32,768 X

echo mixer circuit

Abstract: echo mixer circuit diagram DATASHEET OF IC 741 HT8665 LM324 LM386 audio echo ic
Contextual Info: HT8665 Talking Back with Echo Features • • • • • Operating voltage: 4.5V~5.5V ADM algorithm Auto playback with an echo effect DRAM options: – 64K – 256K Sampling rate options: – 32Kbps bits per second – 16Kbps • • • • • • •

A65H73361

Abstract: A65H83181 SA10 SA11 SA12 SA13 SA15
Contextual Info: A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 PRELIMINARY

K6F2008S2E

Abstract: K6F2008S2E-F
Contextual Info: K6F2008S2E Family CMOS SRAM Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark Preliminary 0.0 Initial Draft February 28, 2001 1.0 Finalize September 27, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

MT55L256L18P1T-10A

Abstract: MS-026 MT55L128L32P1 MT55L128L36P1 MT55L128V32P1 MT55L128V36P1 MT55L256L18P1 MT55L256L18P1T-10 MT55L256V18P1 84 FBGA thermal
Contextual Info: PRELIMINARY 4Mb: 256K x 18, 128K x 32/36 PIPELINED ZBT SRAM 4Mb ZBT SRAM MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3.3V VDD, 3.3V or 2.5V I/O FEATURES • • • • • • • • • • • • • •

A67L7332

Abstract: A67L7336 A67L8316 A67L8318
Contextual Info: A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary LVTTL, Pipelined DBA SRAM Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue

4F256

Abstract: 24LC256 4L256 24lc256 datasheet 24AA256 24FC256 24XX256 G4AD
Contextual Info: 24AA256/24LC256/24FC256 256K I2C CMOS Serial EEPROM Device Selection Table Description Part Number VCC Range Max. Clock Frequency 24AA256 1.8-5.5V 400 kHz 1 I 24LC256 2.5-5.5V 400 kHz I, E 2.5-5.5V 1 MHz I 24FC256 Note 1: The Microchip Technology Inc. 24AA256/24LC256/