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attiny2313 Abstract: attiny2313-20pi CS01 CS02 CS12 WGM10 Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation	Original	16-bit 2543es attiny2313 attiny2313-20pi +4cs01 cs02 cs12 wgm10	PDF

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attiny2313

Abstract: attiny2313-20pi CS01 CS02 CS12 WGM10
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

Original

16-bit 2543es attiny2313 attiny2313-20pi +4

PDF