244 TFK Search Results

TFK diodes BYW 76

Abstract: 13009 Jt 43 byw 56 equivalent TFK diodes 148 tfk U 264 tfk 804 TFK 421 diode BYW 60 diode byt 45 J BYT 45 J
Contextual Info: .4 . 'W iriy IFWCCIRQ electronic Creative Technologies Selection guide transistors and diodes Contents, alpha-numeric Type Page BA 204 BA 243 BA 244 BA 282 BA 283 BA 4 79 G BA 4 7 9 S BA 679 BA 682 BA 683 BA 779 6 6 6 6 6 7 7 7 6 6 7 B A Q 33 BAQ 34 BAQ 35

tfk 19

Abstract: 2x121 TFK S 1 86 P
Contextual Info: N O IE S : U N LESS OTHERWISE SPECIFIED; C A T A L O G N U M B E R D E S C RIPTIO N C B H 2X121S C - V CONNECTOR SERIES C A RD ED G E t B1-% 9 .5 0 Í0 .2 5 .3 7 4 1 .0 1 0 2.835 1.850 7 3 C ON TA C T PAIRS 48 C ON TA C T PAIRS B I -L E V E L CONTACTS J '

ZL50011QCG1

Abstract: GR-1244-CORE MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack

GR-1244-CORE

Abstract: MS-026 ZL50011 11CH marking
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2005 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • September 2011 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information ZL50011/GDC 144 Ball LBGA Trays ZL50011QCG1 160 Pin LQFP* Trays, Bake & Drypack

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

32.768Mhz oscillator

Abstract: FOX 20.000 MHZ GR-1244-CORE MS-026 ZL50011 tfk8
Contextual Info: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features December 2003 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL

filter FP1P

Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

GR-1244-CORE

Abstract: MS-026 ZL50010
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

ZL50010QCG1

Abstract: GR-1244-CORE MS-026 ZL50010 32CH1
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

GR-1244-CORE

Abstract: MS-026 ZL50010 TFPW0
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

FOX 20.000 MHZ

Abstract: LMT 324 slv ca2 GR-1244-CORE MS-026 ZL50010 STO14 tfk8k
Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay

Contextual Info: ZL50010 Flexible 512 Channel DX with Enhanced DPLL Data Sheet Features VDD • • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15 FPo0 CKo0

TFK 548

Abstract: TFK U 217 B IRM1010 SDVC
Contextual Info: Package Outline Part Number Slimline SIP SMD Features Page Mb/s IrDA compatible transceiver that supports data rates of 1 Mb/s down to 9.6 Kb/s. LED power select function in­ cluded. Compact package size: 4.0 mm in height, 9.6 mm in width and 4.5 mm in depth. Selectable LED trans­

tfk8k

Abstract: lg1001 LID17
Contextual Info: MT90866 WAN Access Switch Preliminary Information Features • • • • • • • • • • • • • • • • • • • • • • • • 3.3V operation with 5V tolerant inputs and I/O’s 5V tolerant PCI driver on CT-Bus I/O’s 2,432 x 2,432 non-blocking switching among local

GR-1244-CORE

Abstract: MS-026 ZL50011
Contextual Info: ZL50011 Flexible 512-ch DX with on-chip DPLL Data Sheet Features VDD • • • Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers VSS

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98431 10/100 Mbps Ethernet TM CONTROLLER DESCRIPTION The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control MAC ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the

FD31

Abstract: PD98431 c3194 35x35 bga
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98431 10/100 Mbps Ethernet TM CONTROLLER DESCRIPTION The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control MAC ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the

ZL50010

Abstract: TFR1M GR-1244-CORE MS-026
Contextual Info: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15

renesas BGA 305

Abstract: FD31 NEC AC12 PD98431 FD42
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

processor cross reference

Abstract: TFK 035 U 111 B
Contextual Info: MITSUBISHI SOUND PROCESSOR ICs M62475FP AUTOMATIC ADJUSTMENT CD PREAMPLIFIER SERVO CONTROLLER DESCRIPTION The M62475FP is an 1C that contains preamplifier/servo amplifier necessary for optical pickup servo control for CD player. This 1C also supports automatic adjustment with microcomputer control.

ap1448

Abstract: 45x45 bga an6169 RXFD65 Rxd07 734 B34 8B10B PD98431 C3258 709 B34
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD98433 TM 10/100/1000 Mbps Ethernet Controller The µPD98433 is a 10/100/1000 Mbps Ethernet controller with eight-port internal Media Access Control MAC function that complies with the IEEE Standard 802.3 1998 Edition.

PAR64

Abstract: PD98405GL-PMU diode be2b PD98405 UPD98405GLP WB mark Diode
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98405 155M ATM INTEGRATED SAR CONTROLLER DESCRIPTION The µPD98405 NEASCOT-S20TM is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an