24 L2 Search Results

307-1EA00-0AA0

Abstract: siemens sitop power 40 6ep1437-1sl11 6EP1437-1SL11 PS 307 5A SITOP 6EP1333-1SL11 Siemens 6EP1931-2FC01 siemens sitop power 20 6EP1436-1SH01 6EP1436-1SH01 siemens sitop 6ep1436-1sh01 307-1BA00-0AA0
Contextual Info: SITOP power Bestelldaten Technische Daten basic line 1phasig 24 V/2 A 1phasig 24 V/5 A 1phasig 24 V/10 A Typ basic E 24/2 basic E 24/5 basic E 24/10 basic 5D 24/10 basic 5D 24/20 basic D 24/30 basic D 24/40 Bestell-Nr. 6EP1331-1SL11 6EP1333-1SL11 6EP1334-1SL11

radix-8 FFT

Abstract: DBGA KD 472 M mov CMAC A15B2 sc sf 12A H4 17ER CI23 honeywell hx3000 HX3000
Contextual Info: DSP Architectures RHDSP24 Radiation Hardened Scalable DSP Chip Transform Your WorldTM Data Sheet Real 24 PORT A Imag 24 RHDSP24 Imag 24 24 24 X INPU TB US Y INPUT BU S O U TP U TB US 24 48 Imag 24 Scheduler/ Controller X Y Memory A 24 Memory B 24 System Controls

radix-8 FFT

Abstract: yswa BR17 CI23 radix DSP24 24PORTB DR17 64 point radix 4 FFT dsp24s
Contextual Info: DSP Architectures Transform Your World DSP24 TM High Performance Scalable DSP Chip DSP Architectures Data Sheet Real 24 PORT A Imag 24 DSP24 Imag 24 24 24 X I NP U TB US Y INPUT BU S OUTPU TB US 24 48 Imag 24 Scheduler/ Controller X Y Memory A 24 Memory B

dsp24s

Abstract: radix-8 FFT radix1024 CI23 yswa DSP24 DR01 A28AD br09 BR17
Contextual Info: DSP Architectures Transform Your World DSP24 TM High Performance Scalable DSP Chip DSP Architectures Data Sheet Real 24 PORT A Imag 24 DSP24 Imag 24 24 24 X INPU TB US Y INPUT BU S O U TP U TB US 24 48 Imag 24 Scheduler/ Controller X Y Memory A 24 Memory B

SA2111C

Abstract: SA2111CS 13002 FL SA2111CB 5PNR-5146Y 666SNF-305NK SDIP24-300-1 24MPX 666SNF-306NK VC101-F
Contextual Info: SA2111C 3V AM/FM+MPX SA2111C AM/FM 3V FM SSOP-24-300-0.65 SSOP-24-300-1.0 NEW FCC * NEW FCC SOP-24-375-1.27 SDIP-24-300-1.778 * * FM * FM MPX VCO * AFC * AM * * (VCC=3V Tamb=25°C) SA2111C SDIP-24-300-1.778 ICCq(FM)=9.0mA (Typ.) SA2111CS SSOP-24-300-0.65

Contextual Info: Part Number Index Part no. Page Part no. Page 01P0601 24 AD0670R 10 02P0XXX 24 AD 07XXX 7 0 3 P06 0 3 24 AD071AUK 04P0XXX 24 AD 08XXX 06P0XXX 24 AD09XXX 1771P 145 24 AD0910UK Part no. Page Part no. Page 6 BRLZ-12 15 C12M XXX 31 L Z U S3 X X X LZ U S4 X X X

Contextual Info: AKM AK4524 24-Bit 96kHz Audio CODEC Features 24-bit Stereo Digital-to-Analog Converter DAC - Dynamic range and S/R: llOdB - S/(N + D): 94dB - 128x oversampling - 24-bit 8x interpolation filter - Differential outputs 24-bit Stereo Analog-to-Digital Converter (ADC)

Transistor BC 227

Contextual Info: ML.Ö5711 DDObñBD T 3 3 VPX 3225D, VPX 3224D PRELIMINARY DATA SHEET Contents Page Section Title 5 5 1. 1.1. Introduction System Architecture 9 9 9 10 10 10 11 11 12 12 13 14 15 16 16 16 17 17 17 18 20 20 20 21 21 22 24 24 24 24 24 26 27 28 28 29 29 2. 2.1.

F324

Abstract: 2.1 to 5.1 home theatre circuit diagram 74 hc 589 adaptive filter noise cancellation bc 339 DSP56300 finite impulse response SCR FIR 3 D WL 431 DSP56000 DSP56300
Contextual Info: Technical Data Advance Information DSP56321T/D Rev. 2, 10/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

MPS OUTSIDE BOX PACKING SPECIFICATION

Contextual Info: Technical Data Advance Information DSP56321T/D Rev. 1, 8/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

Contextual Info: Technical Data Advance Information DSP56L307/D Rev. 1, 1/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 16 K x 24 bits or 15 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

HA10

Abstract: PB10 DSP56000 DSP56300 DSP56311
Contextual Info: Technical Data DSP56311/D Rev. 2, 1/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation Unit Six Channel

HP16

Abstract: DSP56000 DSP56300 DSP56301 A2061
Contextual Info: Freescale Semiconductor Technical Data DSP56301 24-Bit Digital Signal Processor 52 6 6 3 Memory Expansion Area Triple Timer Host Interface ESSI SCI X Data Program RAM RAM 4096 x 24 bits 2048 × 24 bits Default (Default) Y Data RAM 2048 × 24 bits (Default)

DSP56000

Abstract: DSP56300 DSP56311 HA10 PB10 DSP56300 finite impulse response
Contextual Info: Technical Data DSP56311/D Rev. 5, 4/2003 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation Unit Six Channel

mz 1532

Abstract: 0.01 MF MEX SERIES CAPACITOR
Contextual Info: Technical Data DSP56311/D Rev. 2, 1/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation Unit Six Channel

SBR 2512

Abstract: DSP56000 DSP56300 DSP56311 HA10 PB10
Contextual Info: Technical Data DSP56311/D Rev. 3, 7/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation Unit Six Channel

DSP56000

Abstract: DSP56300 DSP56L307 HA10 PB10
Contextual Info: Technical Data Advance Information DSP56L307/D Rev. 3, 4/2003 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 16 K x 24 bits or 15 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

Contextual Info: Technical Data DSP56321/D Rev. 9, 2/2004 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation Unit Six Channel

Contextual Info: Technical Data Advance Information DSP56L307/D Rev. 4, 2/2004 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 16 K x 24 bits or 15 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

1K33A

Abstract: mz 1532
Contextual Info: Technical Data Advance Information DSP56L307/D Rev. 2, 7/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 16 K x 24 bits or 15 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

aa1bb

Contextual Info: Technical Data Advance Information DSP56L307/D Rev. 1, 1/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 16 K x 24 bits or 15 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation

1 HP25

Abstract: WL 431 DSP56000 DSP56300 DSP56301 CCD97
Contextual Info: Technical Data DSP56301/D Rev. 7, 2/2004 24-Bit Digital Signal Processor 52 6 6 3 Memory Expansion Area Triple Timer Host Interface ESSI X Data Program RAM RAM 4096 x 24 bits 2048 × 24 bits Default (Default) SCI Y Data RAM 2048 × 24 bits (Default) Peripheral

Contextual Info: ANALOG DEVICES □ 24 X 24-Bit CMOS Multiplier ADSP-1024A FEATURES 24 x 24-Bit Parallel Multiplication 95ns Multiply Time 450mW Power Dissipation with TTL-Compatible CM OS Technology Twos-Complement Data Format Rounding Options at Three Positions Left-Shifts of 0, 1, or 2 Bits on Output

Contextual Info: Technical Data Advance Information DSP56321T/D Rev. 1, 8/2002 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Program RAM 32 K x 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits Address Generation