24 BIT ADC SPI FPGA Search Results

12-bit ADC interface vhdl code for FPGA

Abstract: iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4
Contextual Info: Application Note: Virtex-4 and Virtex-5 FPGAs R XAPP866 v3.0 April 7, 2008 An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs Author: Marc Defossez Summary This application note describes how to interface a Texas Instruments analog-to-digital

Schematic

Abstract: DLP-2232H-SF
Contextual Info: DLP-2232H-SF LEAD FREE USB - MICRONTROLLER - FPGA MODULE FEATURES: • • • • • • • • • • Microsemi/Actel SmartFusion Customizable System-on-Chip cSoC FPGA Internal 100MHz, 32-Bit ARM Cortex™-M3 Microcontroller Subsystem (MSS) Internal 100MHz RC Oscillator-1% Accurate

HSM2822

Abstract: AD9510 ADA4937-1 AN-835 AN-877 AD9284-250EBZ 09085-03
Contextual Info: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9284 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold

Contextual Info: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9284 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold

09085-03

Abstract: jedec package MO-220-VKKD-2
Contextual Info: 8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9284 Data Sheet FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold

spartan 3e vga ucf

Abstract: 512MBDDRx4x8x16 LVCMOS33
Contextual Info: MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide UG257 v1.1 December 5, 2007 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,

written

Abstract: UG230
Contextual Info: Spartan-3E FPGA Starter Kit Board User Guide UG230 v1.2 January 20, 2011 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,

ug230

Abstract: XILINX/SPARTAN 3E STARTER BOARD spartan 3e vga ucf VHDL code for ADC and DAC SPI with FPGA spartan 3 spi flash programmer schematic SPARTAN 3E STARTER BOARD xc2c64a-vq44 vhdl code for lcd of spartan3E M25P16 powertip pc1602
Contextual Info: Spartan-3E FPGA Starter Kit Board User Guide UG230 v1.1 June 20, 2008 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 60 mW per channel at 80 MSPS with scalable power options SNR = 71.5 dBFS to Nyquist SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)

ANSI-644

Abstract: 5011K
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 60 mW per channel at 80 MSPS with scalable power options SNR = 71.5 dBFS to Nyquist SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 60 mW per channel at 80 MSPS with scalable power options SNR = 71.5 dBFS to Nyquist SFDR = 92 dBc (to Nyquist) DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)

Contextual Info: DATA SHEET QF1D512 Simple and versatile FIR engine SavFIReTM APPLICATIONS FEATURES • Industrial Control • Maximum 512-tap symmetric or 256-tap nonsymmetric digital FIR filter with 12 – 24 bit data words and up to 32 bit coefficients • Machine Monitoring

QF1D512

Abstract: adc symmetric 8bit HBM 00-07H
Contextual Info: DATA SHEET QF1D512 Simple and versatile FIR engine SavFIReTM APPLICATIONS FEATURES • Industrial Control • Maximum 512-tap symmetric or 256-tap non- symmetric digital FIR filter with 12 – 24 bit data words and up to 32 bit coefficients • Machine Monitoring

AD193X-SPECIFICATIONS

Abstract: AD1935 AD1936 AD1937 AD1938 AD1939 home theater printed circuit board st-64 AD1935XSTZ AD193X
Contextual Info: 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC AD1935/AD1936/AD1937/AD1938/AD1939 Preliminary Technical Data Features Applications PLL generated 32-192kHz or direct master clock Low EMI design 109 dB DAC/ 107dB ADC Dynamic Range and SNR -94dB THD+N Single 3.3V Supply

AD1974

Abstract: AD1974YSTZ EVAL-AD1974EB OP275
Contextual Info: 4 ADC with PLL, 192 kHz, 24-Bit Codec AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates

Contextual Info: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 Data Sheet FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates

WIDEBAND ULTRASOUND PULSE TRANSFORMER

Contextual Info: FUNCTIONAL BLOCK DIAGRAM AVDD VIN+A VIN–A VIN+B GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD Low power: 55 mW per channel at 65 MSPS with scalable power options SNR = 75.5 dB to Nyquist SFDR = 91.6 dBc (to Nyquist) DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)

Contextual Info: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Preliminary Technical Data 75.5 dBFS SNR to 170 MHz at 250 MSPS @ 2.5 V p-p FS 74 dBFS SNR to 170 MHz at 250 MSPS @ 2.0 V p-p FS 90 dBFS SFDR to 300 MHz at 250 MSPS @ −1 dBFS at 2.5 V p-p FS

Contextual Info: FUNCTIONAL BLOCK DIAGRAM AVDD VIN+A VIN–A VIN+B GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS

ADCL1

Abstract: AD1974 AD1974YSTZ AD1974YSTZ-RL OP275
Contextual Info: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates

48-LEAD

Abstract: AD1974 AD1974YSTZ AD1974YSTZ-RL OP275
Contextual Info: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates

Contextual Info: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates

AD1974

Abstract: AD1974YSTZ OP275 adc1r 5-AD1974
Contextual Info: 4 ADC with PLL, 192 kHz, 24-Bit ADC AD1974 FEATURES GENERAL DESCRIPTION Phase-locked loop generated or direct master clock Low EMI design 107 dB dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates