2308AC1G Search Results

2308AC1G Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
948F Abstract: NB2308A NB2308AC1DG NB2308AC1DR2G NB2308AC1HDG NB2308AI1DG NB2308AI1DR2G Contextual Info: NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks. It is available in a 16 pin package. The part has an on−chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin,	Original	NB2308A NB2308A NB2308A/D 948F NB2308AC1DG NB2308AC1DR2G NB2308AC1HDG NB2308AI1DG NB2308AI1DR2G	PDF
TSSOP16 Abstract: Tape and Reel Packaging Specifications TSSOP-16 SOIC-16 948F NB2308A NB2308AC1D NB2308AC1DG NB2308AC1DR2 NB2308AC1DR2G Contextual Info: NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks. It is available in a 16 pin package. The part has an on−chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin,	Original	NB2308A NB2308A NB2308A/D TSSOP16 Tape and Reel Packaging Specifications TSSOP-16 SOIC-16 948F NB2308AC1D NB2308AC1DG NB2308AC1DR2 NB2308AC1DR2G	PDF

Catalog Datasheet

Type

Document Tags

PDF

948F

Abstract: NB2308A NB2308AC1DG NB2308AC1DR2G NB2308AC1HDG NB2308AI1DG NB2308AI1DR2G
Contextual Info: NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks. It is available in a 16 pin package. The part has an on−chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin,

Original

NB2308A NB2308A NB2308A/D 948F NB2308AC1DG NB2308AC1DR2G NB2308AC1HDG NB2308AI1DG NB2308AI1DR2G

PDF

TSSOP16

Abstract: Tape and Reel Packaging Specifications TSSOP-16 SOIC-16 948F NB2308A NB2308AC1D NB2308AC1DG NB2308AC1DR2 NB2308AC1DR2G
Contextual Info: NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks. It is available in a 16 pin package. The part has an on−chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin,

Original

NB2308A NB2308A NB2308A/D TSSOP16 Tape and Reel Packaging Specifications TSSOP-16 SOIC-16 948F NB2308AC1D NB2308AC1DG NB2308AC1DR2 NB2308AC1DR2G

PDF