2114 RAM IC Search Results

Am91L24

Abstract: AM91L24B 91l24 2114 1k x 4 SRAM Am91L14 2114 1k x 16 RAM 2114 SRAM Am9124 Am9124/Am9114 am91l14 am91l24 AM9124B
Contextual Info: Am9114/9124 Am9114/9124 1024 x 4 Static RAM DISTINCTIVE CHARACTERISTICS • • • • Low operating and standby power Access times down to 200 ns Am9114 is a direct plug-in replacement for 2114 Am9124 pin and function compatible with Am9114 and 2114, plus 5 3 power-down feature

SCM21C14

Abstract: 2114 ram 2114AL-4 ram 2114 2114 static ram 2114 2114 static ram memory memory 2114 STATIC RAM 2114 SCM2114ALM
Contextual Info: SCM2114AL SOLID ^ STATE <§P SCIENTIFIC 1024 x 4 Static CMOS RAM Preliminary Pin Configuration Features i Fast Access Time Selection: 100ns/120ns/150ns/200ns i Direct Replacement for NMOS 2114 RAMs I 883 Qualified Version: 883/2114ALM i Three-State Outputs

2148 static ram

Abstract: 2148 ram ram 2114 D2148 D2148-3 2148 2114 static ram diagram 2114 pin diagram Scans-00105431 2114 ram
Contextual Info: 2148 4096 Bit 1024 X 4 HMOS S ta tic RAM FEATURES GENERAL DESCRIPTION • • • • • • • • The Intersil 2148 is a high speed 4096 bit static RAM or­ ganized 1024 words by 4 bits. It is a single-layer poly HMOS version of the industry standard 2114, and pin compatible

S2114

Abstract: S211 2114L 2114 static ram RAM 2114 vmos S2114-1 S2114-2 S2114-3 S2114A-1
Contextual Info: AMI S 2114 40 96 BIT 1024x4 STATIC V M O S RAM Features G eneral D escription □ High Speed Operation: Access Time: 150ns Maximum (-1 ) The AMI S2114 is a 4096 bit fully static RAM organ­ ized as 1024 words by 4 bits. The device is fully TTL compatible on all inputs and outputs and has a single

2114 static ram

Abstract: ic 2114 RAM 2114 ci 2114 memory ic 2114 2114 2114 ram 2114 static ram ic memory 2114 P2114
Contextual Info: 2114 4096 Bit 1024x4 NMOS Static RAM Ö M Ü f^ D IL FEATURES D E S C R IP T IO N • • • • • • • • The 2114 is a 4096-bit s ta tic R andom A cce ss M em ory organized 1024 w ord s x 4 bits. The s to ra g e c e lls and decode and co n tro l c irc u itry are c o m p le te ly s ta tic , th e re fo re no

91L14

Abstract: cd018 ST 9114 Am91L14
Contextual Info: a Am9114/Am91 L14 AdvS 1024x4 Static RAM Devices DISTINCTIVE CHARACTERISTICS • • • Low operating and standby power Access tim es down to 200 ns Am9114 is a direct plug-in replacem ent fo r 2114 • • High output drive: 3.2-mA sink current @ 0.4 V TTL-kJentical input/output levels

91l14

Abstract: RAM 9114 AM9124 AM91L14C 9114 RAM AM9114 9114 static ram STATIC RAM 2114 AM9114E AM9114B
Contextual Info: A m 9 1 1 4 / A m 9 1 L 1 4 1024x4 Static RAM DISTINCTIVE CHARACTERISTICS Low operating and standby power A ccess times down to 200 ns Am9114 is a direct plug-in replacement for 2114 High output drive: 3.2-mA sink current TTL-identical input/output levels

AM91L148

Abstract: 9114 RAM AM81H 91L14
Contextual Info: A m 9 1 1 4 /A m 9 1 L 1 4 “ " 1024x4 Static RAM S Devices DISTINCTIVE CHARACTERISTICS • • • Low operating and standby power Access times down to 200 ns Am9114 is a direct plug-in replacement for 2114 • • High output drive: 3.2-mA sink current @ 0.4 V

ci 2114

Abstract: 2114L-3 2114L2 2114 static ram 2114 2114 static ram diagram 2114 ram RAM 2114 memory 2114 D2114L RAM
Contextual Info: 2114 4 0 9 6 Bit 1 0 2 4 x 4 NMOS Static RAM M1KR5H. D E S C R IP T IO N FEA TU R ES • Cycle Time Equal to Access Time • Completely Static • No Clock Required • Common Data Input and Output • TTL Compatible Inputs and Outputs • 883A Class B Processing Available

LC3514A-15

Abstract: LC3514AL-15 LC3514AL-20 RAM 2114 2114 Ram pinout 18 LC3514A LC3514AL15K LC3514AL-20K ci 2114 LC3514A15K
Contextual Info: F N o. 2881 i L C 3514A - i 5K,2qk/L C 3514A L - i 5K,20K CMOS LSI 1024 Words X 4 Bits High-Speed CMOS Static RAM G e n e ra l D e sc rip tio n The LC3514A/LC3514AL are fully asynchronous CMOS static RAMs organized as 1024 wordsX 4 bits. They are compatible with worldwide standard N-channel 2114-type 4K SRAMs and have a full CMOS

Contextual Info: Random-Access Memories RAMs MWS5114 a6 — I I8 “ VDD A5 — 2 I7 — A? * 4 - 3 I6 a 3 — 4 I - «8 I5 - A g CMOS 1024-Word by 4-Bit LSI Static RAM Ao — 5 I4 — I/O t Features: A| — 6 I3 — 1 / 0 2 7 I2 - I / O 3 • Fully static operation ■ In d u s try s ta n d a rd 1024 x 4 p in o u t (sam e as p in o u ts fo r 6514, 2114,

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Slave Receive Mode 1 byte Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 receives 1-byte data from the master device in slave receive mode. The frequency of the transfer clock is 100 kHz. Target Device

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Master Receive Mode 1 byte Introduction The H8S/2114 receives 1-byte data from a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114 H8S/2104

2114 static ram

Abstract: 2114 Ram pinout 18 2114 static ram ic 2114 4k x 4 2114 LC RAM 2114 LC 2114 ram 2114 RAM ic 2114 "static RAM" ic 2114
Contextual Info: SANYO SEMICONDUCTOR CORP 7b 7997076 d Ë J 7 ^ 7 07b OGOlTEM SANYO SEM ICO NDUCTOR CORP LC 351 4 f3514L 76C 0 1 9 2 4 c-m os l s i 1024 WORDS X A BITS HIGH-SPEED CMOS STATIC RAM 3 f~ 07 CIRCUIT D R A W IN G NO.40D2 3007A General Description The LC3514/LC3514L are nonclocked CMOS static RAM's organized as 1024 words x 4 bits They are

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Slave Receive Mode 128 bytes Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 receives 128-byte data from the master device in slave receive mode. The frequency of the transfer clock is 100 kHz.

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Slave Transmit Mode 128 bytes Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 transmits 128-byte data to the master device in slave transmit mode. The frequency of the transfer clock is 100 kHz.

Contextual Info: APPLICATION NOTE H8S/2100 Series Interrupt Handling during I2C Communication master receive operation Introduction The H8S/2114 receives 128 bytes of data from a slave device by means of channel 0 of the I2C bus interface. During the communication, interrupts are generated using a free-running timer. The frequency of the transfer clock is 100 kHz.

2161B

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Communication Using a Repeated Start Condition Master Transmit/Receive Operation Introduction The H8S/2114 (master device) transmits 1-byte data to a slave device by means of channel 0 of the I2C bus interface. After transmitting the 1-byte data, the master device generates a repeated start condition and receives 128-byte data

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Master Receive Mode 128 bytes Introduction The H8S/2114 receives 128 bytes of data from a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Slave Transmit Mode 1 byte Introduction By means of channel 0 of the I2C bus interface, the H8S/2114 transmits 1-byte data to the master device in slave transmit mode. The frequency of the transfer clock is 100 kHz. Target Device

Am91L24

Abstract: 2114 static ram memory 2114L 91l24 memory ic 2114 pin out ram 2114L 2114L RAM 91L14 2114 1k x 16 RAM 4096N
Contextual Info: IMPROVED PERFORMANCE WITH THE Am9124 By Alex Shevekov, Paul Liu and Joe Kroeger INTRODUCTION off the top of the chart with a value of about .28mW/bit. Note that the Am91L02C, 2114, 2114L, Am9114C, and Am91L14C are straight lines; their dissipation does not depend on the state of

72V284

Abstract: TA 2104 DN 72284
Contextual Info: 3.3 VOLT VARIABLE WIDTH SUPERSYNC FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations:

Contextual Info: APPLICATION NOTE H8S/2100 Series I2C Master Transmit Mode 1 byte Introduction The H8S/2114 transmits 1-byte data to a slave device by means of channel 0 of the I2C bus interface. The frequency of the transfer clock is 100 kHz. Target Device H8S/2114 H8S/2104

aa1413

Abstract: AA1716
Contextual Info: 3.3 VOLT VARIABLE W IDTH SUPERSYNC FIFO 8 ,1 9 2 x 1 8 or 1 6 ,3 8 4 x 9 16,384 x 18 or 3 2 ,7 6 8 x 9 3 2 ,7 6 8 x 1 8 or 6 5 ,5 3 6 x 9 6 5 ,5 3 6 x 1 8 or 1 3 1 ,0 7 2 x 9 1 3 1 ,0 7 2 x 1 8 or 2 6 2 ,1 4 4 x 9 262,144 x 18 or 524,288 x 9 FEATURES: • Choose among the following memory organizations: