20TTL Search Results

SMD marking code 55A

Abstract: cd551 smd code marking NW
Contextual Info: E 7 7 3 Sflta G 0 0 0 1 Û 3 w • very low profile • ^- - ; • Standard 14 PIN SMD layout TTL Input and outputs Precise and stable delays Reliable hybrid construction No external components required • Fan out 10TTL loads/tap, 20TTL loads/package • Operating temperature 0° to 70°c

CD501A-101

Abstract: CD501A-102 CD501A-103 CD501A-104 CD501A-105 CD501A-106 CD501A-107 20TTL CD501A-110
Contextual Info: DESIGNATRONICS/AUTOMATIC 21E D 5 7 7 3 S â b 00001 70 S TTL input and outputs Precise and stable delays Reliable hybrid construction No external components required Fan out 10TTL loads/tap, 20TTL loads/package Operating temperature 0° to 70°C Storage temperature -55° to +125°

CA601A-101

Abstract: CA601A-102 CA601A-103 CA601A-104 CA601A-105 CA601A-106 CA601A-107 CA601A-108 CA601A-109
Contextual Info: s DESIGNATRONICS/AUTOMATIC SIE D 277350b 00001=13 1 I Integrated circuits per Mil-Std-883B ttl input and outputs Precise and stable delays Reliable hybrid construction No external components required Fan out 10TTL loads/tap, 20TTL loads/package Operating temperature -55°C to +125 °c

CD581A-113

Abstract: CD581A-105 CD581A-107 CD581A-110 CD581A-XXX cd5-8
Contextual Info: DÉSIGNATRONICS/AUTOMATIC EIE » 277350b Q 0Q Q 1Û 5 7 .5;TApp^f Requires minimum mounting space TTL input and outputs Precise and stable delays Reliable hybrid construction No external components required Fan out 10TTL loads/tap, 20TTL loads/package Operating temperature 0° to 70°C

CD561A-101

Abstract: CD561A-102 CD561A-103 CD561A-104 CD561A-105 CD561A-106 CD561A-107 CD561A-108
Contextual Info: 277350b GGQOiai 5 14 PIN, 5:TARJSp«|3S Machine insertable Machine insertable very low profile Leading & trailing edge accuracies TTL input and outputs Precise and stable delays Reliable hybrid construction No external components required Fan out 10TTL loads/tap, 20TTL loads/package

JIS-C-7022

Abstract: JIS-C-5026 JIS-C-5025 C251C TDK SAD-025
Contextual Info: Active Delay Lines SAD Series FEATURES APPLICATIONS • 5-output lumped constant type delay lines with built-in TTL logic elements Fast type . • PLCC28 pin-type surface mounting style. • High-speed and low insertion loss type, due to use of TTLIC74F04.

CA501

Contextual Info: DESIGNATRONICS/AUTOMATIC aiE 277350b D DQOOna T I« i-' Ê^-4vSJSS^S^P." S ^ & 3 5 ä? « I CA501 series M ilita C Y lB S tilte W ü m '»JÎlr^ • > v - > - .y \- ; -, n*s»-.-r \r- £ < -~ ^ t£ y ^ . •-'• a.*- < •y^_.-■:ü-^ ri y," ; ^ -

PIN14

Abstract: dap 001
Contextual Info: DE SI GN A T R O N I O S / AUTOMATIC 21E D 577350b 00001Ô 4 0 i IIS ?;•'’i t s D îg it^ tîê J^ lM ô d u l^ ^ ï^ ^ / i * . - •'■' ■ '•-y' £ y! * £&•fefe?’ •■ * •—:. = *'•* •.>; "-> * _- IP - £¿~T' $g% £sét& $?3 ■.dhxm»áiáigatM^!tm‘ -

marking code SAD

Abstract: JIS-C-7022 1252C JIS-C7022- B-5
Contextual Info: Active Delay Lines SAD Series TDK Active Delay Lines, SAD Series are 5-output lumped constant type delay lines with built-in TTL logic elements Fast type , which have high heat resistance against any soldering methods including flow and reflow soldering.

20MHZ

Abstract: SYC74HCT590
Contextual Info: SYC74HCT590 8-BIT BINARY COUNTERS WITH OUTPUT REGISTERS SYVANTEK Features • • • • • • • • 8-bit Counter With Register Parallel Register Outputs Low power dissipation High Speed Counter Up To 20MHZ High Driving Capability I o l = 24mA, V o l = 0.5V

CD601CR126

Abstract: CD601CR127 CD601CR128 CD601CR129 CD601CR130 CD601CR131 seriel Delay Modules
Contextual Info: - -• *’ ■ '~Â-' -aa i'iÆi.,EÎi: DESIGNATRONICS/AUTOflATIC 21E D 277350b OGQOia? b T- 47-13: if 6 | ^ y | |l | ^ t 3 | i | I '-14 PIN. 10 TAP TTL input and outputs Precise and stable delays Reliable hybrid construction No external com po n en ts required

EDL-050B

Abstract: EDL-040B EDL-060B EDL-070B EDL-080B EDL-090B EDL-100B EDL-110B EDL-120B EDL-150B
Contextual Info: Delay Lines EDL Series Active Delay Lines Lead FEATURES • Waveform shaping circuits are not required for the built-in TTL IC. • Integration into a dual-inline package achieves a compact size only 5.08mm in height. • These delay lines are transfer molded using high-performance

Contextual Info: P C A ELE CT RONIC S INC DSE D | bñSSlO^ DOOOST? ö T~V7-/5 8 Pin SIL Triple TTL Compatible Active Delay Lines DELAY TIME ±5% or ±2 nS s 6 7 8 9 10 11 12 13 14 15 16 17 16 PART NUMBER DELAY TIME ±5% or ±2 nS EP9934-5 EP9934-6 EP9934-7 EP9934-8 EP9934-9

EDL-150

Abstract: edl-150b EDL060B V/smd EDL 63
Contextual Info: Delay Lines ACTIVE DELAY LINES TEST CONDITIONS Input test conditions Signal level Vi V 3.2 Pulse width 3Td Pw Repetition cycle T 10Pw Rise time tr(nsec.) 5 max. Operating voltage Vcc (V) 5 ± 0 .1 Tem perature (°C )[°F ] 2 5 ± 1 [77 ± 1.8] Output load conditions

f959

Abstract: EP9590-200 EP9590-225 EP9590-25 EP9590-250 EP9590-30 EP9590-300 EP9590-35 EP9590-40 EP9590-45
Contextual Info: P C A ELECTRONICS INC SSE D • bfiSElD^ OGOOMfiL. bbb ■ PCA 14 Pin DIL 5 Tap Low Profile i n ­ compatible MIL 883 Active Delay Lines TAP DELAYS ±5% or ±2 nS TOTAL DELAYS ±5% or ±2 nS PART NUMBER TAP DELAYS ±5% or ±2 nS 25 30 35 40 45 50 60 75 100

CRYSTAL-16

Abstract: CO-402C co-401 CO-402B CO-402
Contextual Info: Vectron Products - Custom Hybrid TTL Clock Oscillators - CO-402 Page 1 of 5 Product Search • Home · About Us · What's New · Products · Application Notes · Contact Us · Jobs CO-402 Custom Hybrid TTL Clock Oscillators Products > XOs > CO-402 Features

CD502A-101

Abstract: CD502A-102 CD502A-103 CD502A-104 CD502A-105 CD502A-106 CD502A-107 CD502A-108 CD502A-109 20TTL
Contextual Info: •/>C;i: v -,-: ;V i f i ^ l DESIGNATRONICS/AUTOMATIC SIE D GD502A S6rÎ6S^Â#?i%': •• S K [|îgit:aLDeIa l Modg!e, Mu i11 Delay TTL inputs and o u tp u ts Precise and stable delays Reliable hybrid con struction No external c o m p o n e n ts required

INTEL 2118 DRAM

Abstract: intel 8288 bus controller intel 8203 Intel AP-75 2118 16k intel 8288 INTEL application notes Intel AP-92A Intel 2118 crt terminal interfacing in 8086
Contextual Info: APPLICATION NOTE AP-133 Aprii 1982 V * * < # v <5 V INTELCORPORATION, 1982 y s ¿ ss r O rd*r Number: 210431-001 3-70 PREFACE This application note has been developed to provide the m em ory system designer with a detailed description o f m icroprocessor m emory system design using Intel

SAD-050

Abstract: SAD-020 IC74F04 SAD-100 SAD-150 SAD-075 SAD050 diode sad SAD-025 PLCC28
Contextual Info: Delay Lines SAD Series Active Delay Lines SMD FEATURES • The SAD series are 5-output lumped constant type delay lines with built-in TTL logic elements Fast type • These parts employ the PLCC28 pin-type surface mounting style. • Using the IC74F04 TTL, they achieve high speed and low insertion loss.

SAD-050

Abstract: EDL060B SAD-100 EDL 63 SAD-150 SAD-025 edl100b SAD200 edl-040
Contextual Info: Delay Lines ACTIVE DELAY LINES TEST CONDITIONS Input test conditions 3.2 3Td 10Pw 5 max. 5±0.1 25 ± 1 [77 ± 1.8] Signal level Vi V Pulse width Pw Repetition cycle T Rise time tr (nsec.) Operating voltage Vcc (V) Temperature (°C) [°F] Output load conditions

ADL-050SH

Abstract: ADL-100S adl-060sh ADL-150S ADL250SH ADL-250SH adl12
Contextual Info: ACTIVE DELAY LINES DIP 14-PIN TYPE Built-in TTL, total delay time:20 to 250ns ADL series FEATURES • Waveform shaping circuits are not required for the built-in TTL IC. • Integration into a dual-inline package achieves a compact size only 5.08mm in height.

dap 001

Abstract: H045 CD521A-102 CD521A-101 CD521A-103 CD521A-104 CD521A-105 CD521A-106 CD521A-107 CD521A-108
Contextual Info: D E S I G N A T R O N I C S / A U T OMATIC 21E D 277350b QQ0017T 7 TÎTÎMP î çjl jftiàil D61 aVï M O d u le , 1 ap i n , 5 T A P TTL input and outputs Leading & Trailing Edge Accuracies Precise and stable delays Reliable hybrid construction No external components required

Contextual Info: D E S I G N A T R O N I C S / A U T O M A T I C S I E D 2 7 7 3 5 b G O O ü m fl SeneslM lIltarv aLDelavMQ •r #3 • ê T integrated circuits per Mil-std-883B TTL inputs and outputs Precise and stable delays Reliable hybrid construction No external com ponents required

CD501BR126

Abstract: CD501BR127 CD501BR128 CD501BR129 CD501BR131 CD501BR132 CD501BR133 200i-12
Contextual Info: DESIGNATRONICS/AUTOMATIC. SIE D • 577350b OOOQ1ÖS S £D50i B R iS e rie ^ a p ^ « » ii^ iip ig ita i 0 è l » i c l u i WM& • • • • • TTL input and outputs Precise and stable delays Reliable hybrid construction No external components required