208LEAD Search Results

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

1MD45

Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Contextual Info: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence

CY37384

Abstract: CY37384V L0651
Contextual Info: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.

CFL blast circuit information

Abstract: AM486DX5-133V16BHC kfn 332 smt cpu 486 dx5 TL920 design of 18 x 16 barrel shifter in computer arch 486DX MEMORY CONTROLLER tr3 5m a17
Contextual Info: A M Dii PRELIMINARY Enhanced Am486 DX Microprocessor Family DISTINCTIVE CHARACTERISTICS - Industry-standard two-pin System Management Interrupt SMI for power management indepen­ dent of processor operating mode and operating system - 105.6-million bytes/second burst bus at 33 MHz

Contextual Info: Standard Products ACT 7000ASC 64-Bit Superscaler Microprocessor January 24, 2005 FEATURES • ■ Full militarized PMC-Sierra RM7000A microprocessor Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance

Contextual Info: ID T 7 9 R 4 7 0 0 6 4 -B it RISC M icro p ro cesso r FEATURES * * Low-power operation 3.3V power supply, forthe “RV” part 5Vpower supply, for the “R” part Dynamic power management Standby mode reduces internal power True 64-bit microprocessor 64-bit integer operations

est 7502 b data sheet

Contextual Info: P E H I1 0 IM 1 D B M IV i n Dt t e : s. i 991 82495XP CACHE CONTROLLER/ 82490XP CACHE RAM • Two-Way, Set Associative, Secondary Cache for i860 XP Microprocessor MESI Cache Consistency Protocol ■ 50 MHz “No Glue” Interface with CPU Maintains Consistency with Primary

Contextual Info: 82558 Fast Ethernet PCI Bus Controller with Integrated PHY Networking Silicon Datasheet Product Features • Provides IEEE 802.3/802.3u 10BASE-T and 100BASE-TX compatibility ■ Provides glueless 32-bit PCI bus master interface ■ Contains internal 3 Kbyte transmit and 3

Intel Microprocessor 240440

Abstract: 82360SL intel 82360SL
Contextual Info: in te i November 1992 Intel486 SL Microprocessor SuperSet Data Book Order Number: 241325-001 2-1 Intel486™ SL Microprocessor SuperSet CONTENTS CONTENTS page page 1.0 INTRODUCTION . 2-6 3.0 82360SL I/O SPECIFICATIONS . . . . 2-79

TS PQ4 12

Abstract: TS PQ4 24 ts pq4 10 TS PQ4 20 TS PQ4 120
Contextual Info: in y 1.0 80960HA/HD/HT About This Document This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i960 H x M icroprocessor U ser’s Guide 272484 .

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

1de2

Abstract: northbridge circuit pentium 4 PS/2 KEYBOARD CONTROLLER 001H CY82C691 CY82C693UB intel 8042 keyboard controller 000B0000
Contextual Info: CY82C693UB P R E LIM IN A R Y hyperCache / Stand-Alone PCI Peripheral Controller with USB — CD ROM support Features PCI to ISA bridge PCI Bus Rev. 2.1 compliant Supports up to 5 additional PCI masters including the CY82C691 Integrated DMA controllers with Type A, B, and F sup­

AT91SAM9260B-CU

Abstract: AT91SAM9260B-QU application note SAM9260
Contextual Info: Features • 180 MHz ARM926EJ-S ARM Thumb® Processor – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories • • • • – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC

transistor SMD BR21

Abstract: SMD Transistor W08 adsp-21369ksz smd w04 74 smd code t04 smd code W06 transistor SMD W06 sMD .v05 smd transistor w04 SMD Transistors w06 56
Contextual Info: a SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 333 MHz core instruction rate with unique audiocentric peripherals such as the digital audio interface, S/PDIF

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-21065L SDRAM Controller for Glueless Interface to Low Cost External M em ory @ 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and T w o Timers w ith Event Capture Options Code-Com patible w ith ADSP-2106x Family

Contextual Info: 9Ë GEC PLESSEY F e b r u a r y 1997 PRELIMINARY INFORMATION S E M I C O N D U C T O R S DS4468-2.2 P2800 2K x 64BIT MULTI-PORT CONTENT ADDRESSABLE MEMORY The P2800 2K x 64bit Multi-port Content Addressable Memory CAM is designed for address filtering, routing and

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: <p Preliminary Datasheet FUJITSU S e p te m b e r 1996 V ersion 0.8 MB86681 ATM Switch Element SRE-L FM L/NPD/SRE-L/DS/1223 The FUJITSU MB86681 is a Self-Routing switch Element (SRE-L) for use in ATM switch fabrics. It is ideally suited to applications in a variety of customer premises equipment such

d4184

Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
Contextual Info: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

ACT5270

Abstract: R4700 R5000
Contextual Info: ACT5270 64-Bit Superscaler Microprocessor Features • ■ Full militarized QED RM5270 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle ■ ● Supports ■ ● 133, 150, 200 MHz operating frequencies – Consult Factory for

AMD 486DX embedded

Abstract: Am486 DX instruction set Am486 AM486DX gdt ansi y14.5m-1982 microprocessor in SLOT MACHINE SMM 201 S-15 80286 microprocessor paging mechanism 486DX MEMORY CONTROLLER
Contextual Info: FINAL Am486DE2 8-Kbyte Write-Through Embedded Microprocessor DISTINCTIVE CHARACTERISTICS • High-Performance Design ■ Complete 32-Bit Architecture — 66-MHz operating frequency — Address and data buses — Frequent instructions execute in one clock

pci to isa bridge

Abstract: dock connector docking connector pci isa 82380AB 82380PB PCI-to-ISA
Contextual Info: R Intel 380AB/PB Dock Set Product Overview 82380AB Mobile PCI-To-ISA Bridge MISA 82380PB Mobile PCI-To-PCI Bridge (MPCI) 290558-001 R Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM N K t t ♦ < ij / 5; PRELIMINARY *^ ' CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes