2 BIT PARITY GENERATOR Search Results

DL122

Abstract: MC10160 MC10170
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

Contextual Info: HITACHI/ L O G IC/ AR RA YS /M EN ^5 74 HC180 HD D Ë | 4 4 ^ 5 0 3 001 0425 O 92D 1 0 4 2 5 # 8-bit O dd/Even Parity G enerator/C hecker This universal, monolithic, 9-bit 8 data bits plus 1 parity bit parity generator/checker features odd/even outputs and

IDT74SSTU32865

Abstract: SSTU32865
Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

PHL 99

Contextual Info: 74AC11280 9-BIT PARITY GENERATOR/CHECKER _ SCAS055A - D3201, APRIL 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadable for n-BKs Parity B[ A[ £ ODD [ GND [ 2 EVEN [ NC [ ll * Flow-Through Architecture to Optimize

74HC28

Contextual Info: M74HC280 9-bit parity generator Datasheet - production data • Pin and function compatible with 74 series 280 • ESD performance – HBM: 2 kV – MM: 200 V – CDM: 1 kV SO14 TSSOP14 Description The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate

74F286

Abstract: SN74F286
Contextual Info: SN 54F286, SN 74F286 9-BIT PARITY GENERATORS/CHECKERS WITH BUS DRIVER PARITY I/O PORT D 2 9 3 2 , M ARC H 1 9 8 7 -R E V IS E D JA N U A R Y 1 9 8 9 SN 54F286 . . . J PACKAGE SN 74F286 . . . D OR N PACKAGE • Generates Either Odd or Even Parity for Nine Data Lines

Contextual Info: SNS4F2B0B, SN74F280B 9-BIT PARITY GENERATORSfCHECKERS D 2 9 3 2 , A P R IL 1 9 8 6 - R E V I S E D J A N U A R Y 1 9 8 9 Generates Either Odd or Even Parity for Nine Data Lines SN 54F280B I PACKAGE SN 74F280B . . . D OR N PA CK AG E T O P VIEW I Cascadable for n-Bits Parity

24-042

Abstract: applications of microprocessor in printer TL16C450 TL16C451 TL16C452
Contextual Info: TL16C451, TL16C452 ASYNCHRONOUS COMMUNICATIONS ELEMENTS SLLS053A- D3284, MAY 1989 - REVISED JANUARY 1990 Fully Programmable Serial Interface Characteristics: 5-, 6-, 7-, or 8-Bit Characters Even-, Odd-, or No-Parity Bit Generation and Detection 1-, 1 1/2-, or 2 Stop-Bit Generation

DDR2-800

Abstract: SSTUA32864 SSTUA32866 E6G3
Contextual Info: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

DDR2-800

Abstract: SSTUA32864 SSTUA32866 D12-D17
Contextual Info: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 03 — 7 March 2007 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

SSTUA32864

Abstract: SSTUA32866
Contextual Info: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

Contextual Info: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74SSTU32866 is a low-voltage device with VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,

PI74

Abstract: PI74SSTU32866 Q13A SN74SSTU32866 SSTU32866
Contextual Info: PI74SSTU32866 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer with Parity Product Features Product Description • PI74 SSTU32866 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1,

DDR2-667

Abstract: Q11A SSTUA32866 SSTUA32866EC
Contextual Info: SSTUA32866 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 26 March 2007 Product data sheet 1. General description The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2

DDR2-800

Abstract: Q11A SSTUB32866
Contextual Info: SSTUB32866 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 15 April 2010 Product data sheet 1. General description The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2

Contextual Info: 74SSTUB32868A www.ti.com SCAS846B – JULY 2007 – REVISED NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • 1-to-2 Outputs Support Stacked DDR2 DIMMs

DDR2-800

Abstract: Q19A SSTUB32866
Contextual Info: SSTUB32865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications Rev. 03 — 27 March 2007 Product data sheet 1. General description The SSTUB32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory modules. It

DDR2-800

Abstract: SSTUA32866 SSTUB32866 ic PRESSURE SENSOR
Contextual Info: SSTUP32866 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs Rev. 02 — 14 September 2006 Product data sheet 1. General description The SSTUP32866 is a 1.8 V configurable register specifically designed for use on DDR2

DDR2-667

Abstract: SSTUA32864 SSTUA32866 SSTUA32S865 TFBGA160
Contextual Info: SSTUA32S865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 Product data sheet 1. General description The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory

TSSOP14

Abstract: 74LVQ280 74LVQ280M 74LVQ280MTR 74LVQ280TTR
Contextual Info: 74LVQ280 9 BIT PARITY GENERATOR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 8 ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

Contextual Info: M54HC280 M74HC280 SGS-THOMSON ilo 9-BIT PARITY GENERATOR HIGH SPEED tPD = 26 ns TYP. at VCc = 5V LOW POW ER DISSIPATION lc c = 4 (MAX.) at TA = 2 5 °C 6V HIGH NOISE IM M U N ITY V n ih = V n i L = 28% VCc (MIN). 1 O UTPUT DRIVE CAPABILITY 10 LSTTL LOADS

baudrate

Abstract: UART DESIGN
Contextual Info: iniUART data sheet Features: • Configurable Transfer Rate: 1200bps to 115.2kbps with Accuracy Better than 0.1% from 8MHz Clock! • Data Format: 7, 8 Bits • Parity Enable, Odd/Even, Error Detection • Stop Bit: 1, 2 Bits • Format Check • 3-Point Input Sampling, Glitch Rejection

74AS280

Abstract: 54ALS280 500NT
Contextual Info: TE X A S IN ST R -CLOGICJ fil ~Q§Qf723 T E X A S De| 0^1753 IN S T R LOGIC 00420^ S |~ Df- Y S ~/7 81 Ç 4 2 8 9 6 SN54ALS280, SN54AS280, SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982 - REVISED MAY 1986 SN 54A LS2 80, SN 5 4 A S2 8 0 . . . J PA C K A G E