2 BIT PARITY GENERATOR Search Results

OB-90

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.

MC10170

Abstract: MC10160 MC10170FN MC10170L MC10170P
Contextual Info: MC10170 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate

Contextual Info: 74AC11286 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS _ D3165, AUGUST 1988 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadabie for n-Bits Parity B[ 1 At 2 * Direct Bus Connection for Parity

MC10170

Abstract: T315 MC10170L
Contextual Info: MC10170 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate

DL122

Abstract: MC10160 MC10170
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9+2-Bit Parity Generator/ Checker MC10170 The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays.

KAG 17 127

Contextual Info: M M O T O R O LA Military 10570 9 + 2-Bit Parity Generator-Checker ELECTRICALLY TESTED PER: MPG 10570 The 10570 is a 11-bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9-bits; that is, Output A go e s high

Contextual Info: SN 54 A S286 , SN 74 A S286 9 BIT PARITY GENERATORS/CHECKER WITH BUS DRIVER PARITY 110 PORT D 2 8 0 9 , DECEM BER 1 9 8 3 - • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Direct Bus Connection for Parity Generation

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

ICS98ULPA877A

Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

Contextual Info: HITACHI/ L O G IC/ AR RA YS /M EN ^5 74 HC180 HD D Ë | 4 4 ^ 5 0 3 001 0425 O 92D 1 0 4 2 5 # 8-bit O dd/Even Parity G enerator/C hecker This universal, monolithic, 9-bit 8 data bits plus 1 parity bit parity generator/checker features odd/even outputs and

IDT74SSTU32865

Abstract: SSTU32865
Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input

Contextual Info: ADVANCE INFORMATION SN 54F280A, SN 74F2B0A 9 BIT PARITY GENERATORS/CHECKERS 0 2 9 3 2 , M AR C H 1 9 8 7 Generates Either Odd or Even Parity for Nine Data Lines SN 54F2B0A . . J PACKAGE SN 74F280A . . . D OR N PACKAGE TOP VIEW Cascadable for n-Bits Parity

s286

Contextual Info: SN54AS286, SN74AS2B6 9 BIT PARITY GENERATORS/CHECKER WITH BUS DRIVER PARITY I/O PORT D 2 8 0 9 , DECEMBER 1 9 8 3 ~ REVISED AU G U S T 1 9 8 5 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity S N 54A S286 . . J PACKAGE

Contextual Info: X41 Typa Number Function No. of Pins TC74AC258 TC74AC273 TC74ACT273 TC74AC280 TC74ACT280 QUAD 2-TO-1 MULTIPLEXER 3-STATE/INV. OCTAL D-TYPE FLIP-FLOP WITH CLEAR OCTAL D-TYPE FLIP-FLOP WITH CLEAR 9-BIT PARITY GENERATOR/CHECKER 9-BIT PARITY GENERATOR/CHECKER

54HC280

Contextual Info: S N 54H C 280, SN74HC2B0 9 BIT ODDIEVEN PARITY GENERATORSfCHECKERS D 2 6 6 4 , DECEMBER I 9 8 2 -R E V IS E D JUNE 19B9 • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits • Can Be Used to Upgrade Existing Systems Using MSI Parity Circuits

PHL 99

Contextual Info: 74AC11280 9-BIT PARITY GENERATOR/CHECKER _ SCAS055A - D3201, APRIL 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadable for n-BKs Parity B[ A[ £ ODD [ GND [ 2 EVEN [ NC [ ll * Flow-Through Architecture to Optimize

XLXX

Abstract: SSTE32882 dba1 SSTE32882HLB JESD8-11A
Contextual Info: DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the

Contextual Info: 54AC11280, 74AC11280 9-BIT PARITY GENERATORS/CHECKERS T I0 1 17— 0 3 2 0 1 . APRIL 1989— REVISED MARCH 1990 • Generates Either Odd or Even Parity for Nine Data Lines 54AC1120O . J PACKAGE 74AC11280 . . . D OR N PACKAGE TOP VIEW • Cascadable for n-Blts Parity

l0610

Abstract: 3 bit parity generator 93S43 93S62 D114 D115 D116 D117 D118 binary multiplier 9344
Contextual Info: FAIRCHILD DIGITAL ARITHMETIC OPERATORS Logic/Connection Diagram Power Dissipation mW Typ M ultiplier 9344 Binary 4x2-Bit 4x2 30 550 D114 4M,6N,9N 2 M ultiplier 93S43 2s Complement 4x2 20 490 D115 4M,6N,9N 3 Parity Generator/Check 54/74180 8-Bit Parity Gen/Check

Parity Generators

Abstract: SN74 SN74ALS280 SN74AS280 SV10 cs86 I80-S
Contextual Info: SN74ALS280, SN74AS280 9-BIT PARITY GENERATORS/CHECKERS D2661, DECEMBER 1982-R E V IS E D M AY 1986 Generates Either Odd or Even Parity for Nine Data Lines S N 7 4A L S 2 80 , S N 7 4 A S 2 8 0 . . . D O R N PACKAGE TO P V IE W Cascadabie for n-Blts Parity

silego

Abstract: Silego Technology D8-D13 D8-D25 Q11A SSTUB32866 lfbga-96ball SLGSSTUB32866B
Contextual Info: SLGSSTUB32866 DDR2 Configurable Registered Buffer With Parity Applications: • DDR2-400/533/667/800 memory modules • 1:1 25-bit or 1:2 14-bit configurable registered buffer with parity • Able to cascade with a second SLGSSTUB32866 • 1.8V data registers

74HC28

Contextual Info: M74HC280 9-bit parity generator Datasheet - production data • Pin and function compatible with 74 series 280 • ESD performance – HBM: 2 kV – MM: 200 V – CDM: 1 kV SO14 TSSOP14 Description The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate

7103

Abstract: ICS98ULPA877A IDT74SSTUBH32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Description The IDT74SSTUBH32865A includes a parity checking function. The IDT74SSTUBH32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

Contextual Info: TEXAS INSTR {LOGIC} OLE D | a ^ i 7 2 3 DD7ai2T □ | SN54F280B, SN74F280B 9-BIT PARITY GENERATORS/CHECKERS T 'V ^ / 7 D2932, APRIL 1 9 8 6 -R E V IS E D M A RC H 19B8 • Generates Either Odd or Even Parity for Nine Date Lines • Cascadable for n-Bits Parity