1XXXA Search Results

laser DFB 1350nm

Abstract: 1350nm 1270nm DFB Laser Diode 1510nm
Contextual Info: 1.27um-1.61um MQW-DFB Laser Diodes for CWDM C-1XXXA-DFB-E-xxx-NT Absolute Maximum Rating Tc=25ºC Parameter Symbol Value Unit Po 8(CW) mW VRLD 2 V LD Forward Current IFLD 150 mA PD Reverse Voltage VRPD 15 V PD Forward Current IFPD 2.0 mA Operating Temperature

laser DFB 1350nm

Abstract: 1350nm
Contextual Info: 1.27um-1.61um MQW-DFB Laser Diodes for CWDM C-1XXXA-DFB-E-XX-NT Absolute Maximum Rating Tc=25ºC Parameter Symbol Value Unit Optical Output Power Po 8(CW) mW LD Reverse Voltage VRLD 2 V LD Forward Current IFLD 150 mA PD Reverse Voltage VRPD 15 V PD Forward Current

GR-468-CORE

Contextual Info: P/N: C-1XXXA-DFB2.5-PX-SSCXI-03-XX CWDM Series 2.5G Laser Diode Module 18 channel Features l Un-cooled laser diode with MQW structure l High temperature operation without active cooling l Hermetically sealed active component l Built-in InGaAs monitor photodiode

upc 1270 H

Abstract: 1XXXA 1XXXX laser diode 1550 nm xxSxx
Contextual Info: Reference No: OM-D-SP-0001-V14 Date: 2003/8/21 Specifications Product Part Name: Product (Part) No: 2.5G CWDM Series Laser Diode Module (18 channel) C-1XXX-DFB2.5-T/R/PX-SXXXI/XXX-X ; C-1XXXA-DFB2.5-T/R/PX-SXXXI/XXX-X Revision record Version Issue date Description of change

Contextual Info: HIGH-SPEED 3.3V 64K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9089S/L In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • • • • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location

Contextual Info: PRELIMINARY IDT70V908S/L HIGH-SPEED 3.3V 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM Bvsp \dt integrated Device Technology, Inc. FEATURES: • • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • High-speed clock to data access

Contextual Info: HIGH-SPEED 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709269S/L Integrated Device Technology, Inc. FEATURES: • • • • • • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location High-speed clock to data access

A0L-A12L

Abstract: A12L CY7C09349A CY7C09349A-12AC CY7C09349A-6AC CY7C09349A-7AC CY7C09349A-9AC CY7C09359A CY7C09359A-6AC IND5
Contextual Info: - - = CYPHhbo CY7C09349A PRELI MI NARY_ CY7C09359A = 4K/8K x 18 Synchronous Dual-Port Static RAM High-speed clock to data access 6.5l1V7.5/9/12 ns max. Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location

Contextual Info: HIGH-SPEED 32K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709279S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: Full synchronous operation on both ports - 4ns setup to clock and 1 ns hold on all control, data, and address inputs

Contextual Info: HIGH-SPEED 3.3V 1 6 K x 1 6 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9269S/L In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • True Dual-Ported m em ory cells which allow sim ulta­ neous access of the sam e m em ory location

Contextual Info: HIGH-SPEED 16Kx 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709269S/L Integrated Device Technology, Inc. FEATURES: • • True Dual-Ported m em ory cells which allow sim ulta­ neous access of the sam e m em ory location • H igh-speed clock to data access

Contextual Info: HIGH-SPEED 3.3V 32K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9079S/L In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • True Dual-Ported m em ory cells which allow sim ulta­ neous access of the sam e m em ory location

Contextual Info: HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9269S/L Features: * * a cce ss of the sam e memory location Full synchronous operation on both ports High-speed clock to data acce ss - - * additional logic True Dual-Ported memory cells which allow simultaneous

Contextual Info: HIG H -SPE ED 32K x 16 S Y N C H R O N O U S PI PELINED D U A L - P O R T STATIC RAM PRELIMINARY IDT709279S/L FEATURES: • • • • • • • True Dual-Ported m em ory cells which allow sim ulta­ neous access ot the sam e m em ory location High-speed clock to data access

Contextual Info: HIGH-SPEED 64K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709089S/L I n t e g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • • • • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location

Contextual Info: HIGH-SPEED 3.3V 1 6 K x 1 6 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9269S/L FEATURES: • True Dual-Ported m em ory cells which allow sim ulta­ neous access of the sam e m em ory location • H igh-speed clock to data access — Com m ercial: 9/12/15ns max.

A12L

Abstract: CY7C09349AV CY7C09359AV hcn 73 1016l 75l1 75L12
Contextual Info: CYPRESS CY7C09349AV CY7C09359AV PRELIMINARY 3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM • High-speed clock to data access 7.5l1’ 2V9/12 ns max. • 3.3V Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location

Contextual Info: HIGH-SPEED 3.3V 3 2 K x 1 6 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V9279S/L I n te g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: Full synchronous operation on both ports - 4ns setup to clock and 1 ns hold on all control, data,

bU1011

Abstract: 026R ca2dc CY7C09569V
Contextual Info: CY7C09569V CY7C09579V PREUM INAm 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM 3.3V Low operating power Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location • 2 Flow-Through/Pipelined devices

PLCC44

Abstract: 80251G
Contextual Info: Tem ic Semiconductor s Extended 8-Bit Microcontrollers C251 Family Part Number j Function / Application Key Features Package Extended 8-bit Microcontrollers TSC80251A1 Extended 8-bit microcontroller with analog interfa­ ces PMU. EW C, 8 24 Kb OTP/ROM , 1 Kb RAM . 2 x 16-bit timers,

Contextual Info: HIGH-SPEED 32K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709079S/L In te g ra te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • True Dual-Ported m em ory cells which allow sim ulta­ neous access of the sam e m em ory location

CY7C09569V

Abstract: CY7C09579V
Contextual Info: # CYPRESS CY7C09569V PRELIMINARY _ CY7C09579V 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM 3.3V Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location • Two Flow-Through/Pipelined devices

CY7C09569V

Contextual Info: ! ^ '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- J M N K ♦ < ij / CY7C09569V CY7C09579V PRELIMINARY 5; 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM 3.3 V Low o p e ratin g p ow er Features — A c tiv e = 165 m A typ ical • True D u al-P o rted m e m o ry cells w h ich allo w s im u lta ­

Contextual Info: r- = CYPHhbo CY7C09349 PRELIMINARY_ CY7C09359 = 4K/8K x 18 Synchronous Dual-Port Static RAM High-speed clock to data access 6.5l1V7.5/9/12 ns max. Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location