1K TRANSMIT BUFFER Search Results

200B

Abstract: 24LC41A
Contextual Info: 24LC41A 1K/4K 2.5V Dual Mode, Dual Port I2C Serial EEPROM PACKAGE TYPE PDIP Upon power-up, the DDC Monitor Port will be in the Transmit-Only Mode, repeatedly sending a serial bit stream of the entire memory array contents, clocked by the VCLK pin. A valid high to low transition on the DSCL

OSC 125MHz

Abstract: U17E AX88655 AX88655P CRYSTAL 27MHZ 8c350 AT24C16B
Contextual Info: AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5-Port Gigabit Ethernet Switch with Embedded Memory Document No.: AX88655-1.0 / V1.0 / Mar, 12,2002 Features • • • • • • • • • 5-Port Gigabit Ethernet switch integrating MACs, packet buffer memory and switching engine with

HFA3726

Abstract: HFA3824 SSB Modulator application note suppression filter MC-104M50-7U08-NI AN9746 AN9746.2
Contextual Info: Using the PRISM HFA3726EVAL Evaluation Board Application Note March 2000 AN9746.2 Author: Raphael L. Matarazzo Introduction band operation, the Local Oscillator frequency input is required to be twice the desired frequency for modulation/demodulation. A buffered, divide by 2, LO single ended

evm1ss

Abstract: Frequency Doubler 30Mhz AN9746 9746 PCC103BQCT-ND LL1608-F10NK HFA3726 HFA3824 HFA3825 schematic diagram pulse shaping
Contextual Info: Using the PRISM HFA3726EVAL Evaluation Board Application Note June 1998 AN9746.1 Author: Raphael L. Matarazzo Introduction band operation, the Local Oscillator frequency input is required to be twice the desired frequency for modulation/demodulation. A buffered, divide by 2, LO single ended

high impedance rf voltmeter circuit diagrams

Abstract: 08GS HFA3724 HFA3824 HSP3824 evm1ssx50 ic tester AC digital voltmeter diagram bead 500kHz IND FXD
Contextual Info: Using the PRISM HFA3724EVAL Evaluation Board Application Note August 1998 AN9622.1 Author: Raphael L. Matarazzo Introduction modulation/demodulation. A buffered, divide by 2, LO single ended 50Ω selectable output is provided for convenience of PLL designs. The receive down converter

st 9622

Abstract: IC Generator to 2MHz square LL1608-F10NK HFA3724 HSP3824 evm1ssx50
Contextual Info: Using the PRISM HFA3724EVAL Evaluation Board TM Application Note March 2000 AN9622.2 Author: Raphael L. Matarazzo Introduction modulation/demodulation. A buffered, divide by 2, LO single ended 50Ω selectable output is provided for convenience of PLL designs. The receive down converter mixers “I” and “Q”

78Q8392

Contextual Info: SSI 78Q8392 ó m m s is k m A TDK Group/Company Ethernet Coaxial Transceiver s December 1994 DESCRIPTION FEATURES The SSI 78Q8392 Ethernet Transceiver is a high speed, bipolar coax line transmitter/receiver.The device includes analog transmit and receive buffers, a 10 MHz

aui isolation transformer

Abstract: 78Q8392L-28CH 78Q8392L 78Q8392L-CP
Contextual Info: 78Q8392L Low Power Ethernet Coaxial Transceiver February 1998 DESCRIPTION FEATURES The 78Q8392L Ethernet Transceiver is a low power BiCMOS coax line transmitter/receiver. The device includes analog transmit and receive buffers, a 10 MHz on-board oscillator, timing logic for jabber and

78Q8392L-28CH

Abstract: 78Q8392L 78Q8392L-CP RR23
Contextual Info: 78Q8392L Low Power Ethernet Coaxial Transceiver February 1998 DESCRIPTION FEATURES The 78Q8392L Ethernet Transceiver is a low power BiCMOS coax line transmitter/receiver. The device includes analog transmit and receive buffers, a 10 MHz on-board oscillator, timing logic for jabber and

FSK modulator and demodulator

Abstract: bpsk modulator transceiver fsk tone encoder Z87000 Z8700000ZEM Z87010 Z87100 Z87200 bpsk modulator direct cordless phone design
Contextual Info: Block Diagram Wi reless Devices DSP C00 CORE ADCs & DACs Device Zilog Superintegration Pr oducts Guide FSK Modulator FSK Demodulator DSP (C00 CORE) 512 Word RAM CODEC Interface TX / RX Buffer Transceiver Control Logic 4KW ROM Data I/O Counter/ Timer 1K byte

REALTEK SEMICONDUCTOR

Abstract: 128 QFP 14x20 RTL8308 24LC02 realtek ethernet programming txe 3x 103 24lc02 datasheet Ethernet Switch Controller
Contextual Info: RTL8308 8-port 10/100 Ethernet Switch Controller with Embedded Memory RTL8308 8-Port 10/100 Ethernet Switch Controller with Embedded Memory The RTL8308 chip is a 128-pin low cost and ultra low power consumption 8-port 10/100M Ethernet switch controller integrated both with a 2M bits embedded DRAM as packet buffer

micrel KS8995

Abstract: KS8995 ks8995e YCL PH406466 802.1q trunk HB726-1 AT24C01A H1164 HB826-2 micrel mii
Contextual Info: KS8995E Micrel KS8995E 5-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 1.10 On the media side, the KS8995E supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced

automatic WATER LEVEL pump CONTROL

Abstract: chilled water system
Contextual Info: Data Sheet, Revision 3 September 21, 2005 TSI-1 1k x 1k Time-Slot Interchanger 1 Introduction The last issue of this data sheet was August 31, 2005. A change history is included in Section 11 Change History on page 61. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text

RXD03

Contextual Info: Data Sheet May 27, 2005 TSI-1 1k x 1k Time-Slot Interchanger 1 Introduction This document consists of two major sections: „ The TTSI001041 device hardware description. This section contains ball information, operating conditions, dc electrical characteristics, timing diagrams, ac characteristics, and packaging information.

KS8993

Abstract: RJ754-C-NL KS8993I KSZ8993 PV32 center tap transformer H1060 pulse h1012
Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.05 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

kendin ks8993

Abstract: KS8993 MICREL PQFP DATE CODE reverse MII timing
Contextual Info: CONFIDENTIAL INFORMATION REV 1.16 KS8993 3 port 10/100 Integrated Switch with PHY and Frame Buffer Highlights • • • • • • • • • • • • • • • • • • • • • • 3 port 10/100 Integrated Switch with Physical Layer Transceivers

RJ754-C-NL

Abstract: 16Kx32 pulse h1012 HB614-1 KS8993 RJ754 reverse MII timing YCL Transformer PH406080 KSZ8993
Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

KS8993

Abstract: RJ754-C-NL KS8993I PV32 ycl 20pmt04 center tap transformer pulse h1012
Contextual Info: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.04 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through

RJ45 1000M PHY

Abstract: 88E1000 AMD79C901 88E3081 49fct3807 CRS15 rmii trace layout guidelines
Contextual Info: ZLAN-86 Ethernet Switch Ethernet Interfaces Reference Design Application Note Contents January 2004 3.3.1 M_CLK 3.3.2 G_REFCLK 3.3.3 10/100 MHz Ethernet Physical layer 3.3.4 Gigabit Ethernet Physical layer 1.0 Introduction 2.0 Interface Overview 2.1 Fast Ethernet

HT6570

Abstract: Ht6550a HT6571 NE558 interface fdd 720k RP4A RP3D
Contextual Info: HT6551 Super I/O Controller Features • • • • 100% compatible to IBM PC AT/XT Fully IBM–BIOS compatible floppy disk controller – 48mA floppy drive interface buffers – Support two floppy drives with capability of supporting up to four drives with an

RJ754-C-NL

Abstract: KS8995 HB826-10 RJG4-754-C-NL H1117 3.3v micrel KS8995 HB826 RJ754-C
Contextual Info: CONFIDENTIAL INFORMATION INFORMATION CONFIDENTIAL REV 1.24 1.24 REV KS8995 5 port 10/100 Integrated Switch with PHY and Frame Buffer Highlights • • • • • • • • • • • • • • • • • • • • • 5 port 10/100 Integrated Switch with Physical Layer Transceivers

KS8997

Abstract: 128-PIN PQFP
Contextual Info: KS8997 Product Brief 8 Port 10/100 Integrated Switch with PHY and Frame Buffers Introduction • The KS8997 contains eight 10/100 physical layer transceivers, eight MAC Media Access Control units with an integrated layer 2 switch. The device runs as an eight port integrated switch.

Contextual Info: SSI 78Q8392 SiliconSifskms Ethernet Coaxial Transceiver A TDK Group/Company December 1994 DESCRIPTION FEATURES The SSI 78Q8392 Ethernet Transceiver is a high speed, bipolar coax linetransmitter/receiver. The device includes analog transmit and receive buffers, a 10 MHz