1I11I Search Results

data image LCD 16x2

Abstract: 16x2 COG 16X2 LCD TIMING CHARACTERISTICS OS22 C175 COG 16x2 lcd pin 16x2 serial lcd COG 16x2 lcd COG 16X2 CHARACTER
Contextual Info: UNCONTROLLED DOCUMENT SC:1 PART NUMBER REV. LCM —H01 6 0 2D 39 86 8LC PRELIM INARY IN P / N DIR DETAIL A <r 1I11I I i— i_ < f 00 g <L [0 .3 9 4 ] [0 .4 3 3 ] [0 .4 7 2 ] [0 .5 7 4 ] —71.00 [2 .7 9 5 ] -— 5É.00 [2 ,2 0 5 ] — — 54,00 C212&] —

MB87030

Abstract: sdb01 SDB03
Contextual Info: FUJITSU SCSI PROTOCOL CONTROLLER MB87030 A p ril 1986 E d itio n 1.0 DESCRIPTION The MB87030 SCSI Protocol C ontroller SPC is a CMOS LSI c ircuit specifically designed to control a Small C om puter Systems Interlace (SCSI). The SPC can serve as either an Initiator or Target fo r the SCSI; thus, it can be used as an I/O

Aleph os-3402

Abstract: Aleph International OS-3302 OS-3402 Aleph aleph OS 3402 OS 3402 A14J OS3302 aleph 3402
Contextual Info: ALEPH INTERNATIONAL CORP jna^» D I 047310? QQDDOSS 4 I interruptor-iype Hnotosensors O S-3302/3402 •Low -cost slit type f J @ t_ -.; - ^ 7 “7 • Features ' The OS-3302 and OS-3402 are visible light cutofftype photosensors which use a GaAs infrared emit­

Contextual Info: RESISTORS D'sp B p s :;ixn> STYLE R EXAM PLE: CR 1 0 0 -2 0 0 - 100 S T Y L E - 1 S I Z E - T h e p a r t n u m b e r is a co m b in atio n o f style, size, w a tta g e , terminal material, value and tolerance. WAt t a g

Contextual Info: Tem ic 29C318 MATRA MHS E l NIU / ISDN PRI Transceiver Description The 29C318 is the first fully integrated transceiver for El NIU and ISDN Primary Rate Interface ISDN PRI applications at 2.048 MHz. This transceiver operates over 2 km of 0.4 mm twisted-pair cable without any

SAA5020

Abstract: SAA5010 SAA5012
Contextual Info: Signetics SAA5050/55 Teletext Character Generator Product Specification Linear Products DESCRIPTION The SAA5050 series of MOS N-channel integrated circuits provides the video drive signals to the television receiver necessary to produce the teletext/view­

CD4024A

Contextual Info: II CD4024A Typ s COS/MOS 7-Stage Binary Counter With Buffered Reset The RCA•C04024A consists of an INPUT PULSE shaping circuit, RESET line driver circuitry, and seven binary counter stages. The counter is reset to "zero" by a high level on the RESET input. Each counter stage is a

8051 internal structure

Abstract: intel MCS-51 ap-69 intel 8751 architecture keyboard controller intel 8048 8048 asm example MCS-511 ic 8039 cpu 8051 interface 8155 intel MCS-48 5LT 6C
Contextual Info: m ie i APPLICATION NOTE AP-69 May 1980 o a P '< > s y A V o 4 $ a ° ^ < -° V e 00° ,<P V5 # € lntel C orporation 1980 AFN-01502A-01 AN IN TR O D U C TIO N TO THE INTEL MCS-51 SING LE-CHIP M ICROCOM PUTER FAMILY Contents 1. IN TR O D U C TIO N . 1

CXD 1130

Contextual Info: SONY CXD2443Q Timing Generator for LCD Panels Description The CXD2443Q is a timing generator for the LCD panel LCX011 and LCX019 driver. This chip has a built-in serial interface circuit which allows various settings to be performed through external control