19B8 Search Results

IC 7422

Abstract: 7422 74LS22D as 5422 T3228
Contextual Info: SN5422, SN 54LS22, SN54S22, S N 7422 , S N 74 LS 2 2 , SN 74S22 D U A L 4-INPUT POSITIVE N A N D G A TES W ITH O P EN C O LLEC TO R O U TPU TS DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Small Outline” Packages, Ceramic Chip Carriers

IC 74LS153

Abstract: 74153 mux cd 74153 ic 74153 IC - 74LS153 74LS153 8 to 1 mux 74LS153 74153 74s153 2C011
Contextual Info: SN54153, SN 54LS153, SN 54S1S3 S N 74153, SN 74LS153, SN 74S153 DUAL 4 LINE TO 1-LINE DATA SELECTORSfM ULTIPLEXERS D E C E M B ER 1972 - R E V IS E D M A R C H 19B8 Permits Multiplexing from N lines to 1 line S N 54153, SN 5 4 LS1 5 3 , SN 5 4 S1 5 3 . . . J OR W

two 7485

Abstract: 74s852 74s85 ic 7485 SN74B5
Contextual Info: SN5485, SN54LS8S, SN54S85 SN7485, SN74LS85, SN74S85 4-BIT MAGNITUDE COMPARATORS MARCH 1974 - R EV ISED MARCH 19B8 TYPE TYPICA L POWER DISSIPATION TYPICA L DELAY 4-BIT WORDS S N 5 4 8 5 . S N 5 4 L S 8 5 , S N 5 4 S 8 5 . . . J OR W P A C K A G E SN 7485 . . . N PACKAGE

s433

Abstract: 74LS33 IC 7433
Contextual Info: SN 5433, SN 54LS33, SN 7433, SN 74 LS3 3 QUADRUPLE 2 INPUT POSITIVE-NOR BUFFERS WITH OPEN COLLECTOR OUTPUTS DECEMBER 1983-REVISED MARCH 19B8 S N 5 4 3 3 , S N 5 4 L S 3 3 . . J OR W PAC KA G E S N 7433 . . N P AC KA G E SN 74LS33 . . D OR N P AC KA G E TO P V IE W

Contextual Info: SMJ27C210 1 048576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SM G S028A — MARCH 19B8 — REVISED N O VEM BER 1990 J Package Top View Single 5-V Power Supply Operationally Compatible With Existing Megabit EPROMs 40-Pln Dual-In-line Package All Inputs and Outputs Fully TTL

K12D

Contextual Info: SN54S134, SN74S134 12-INPUT POSITIVE NANO GATES WITH 3-STATE OUTPUTS DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs S N 5 4 S 1 3 4 . . . J OR W PACKAGE

sn74s350

Contextual Info: SN 54S350, SN 74S350 FOUR BIT SHIFTER WITH THREE STATE OUTPUTS D 2 7 4 5 . DECEMBER 19B3 - Shifts 4- Bits of Data to 0, 1, 2 or 3 Places Under Control of Two Select Lines REVISED M AR C H 19B8 S N 54S 350 . . . J PACKAGE SN 74S 350 . . . D OR N PACKAGE TOP VIEW

Contextual Info: ECL 4 0 9 6 -B IT BIPOLAR SELF-TIM ED RANDOM ACCESS MEMORY FU JITSU MBM10476RR-9 D e c e m b e r , 19B8 Edition 1 .0 4096-BIT BIPOLAR SELF-TIMED RANDOM ACCESS MEMORY T h e Fujitsu M B M 1 0 4 7 6 R R -9 Is fully d e o o d e d 4 0 9 6 -b it E C L s e lf-tim e d r e a d /w r ite

2132G

Abstract: TI0121
Contextual Info: 54ACT11353, 74ACT11353 DUAL 1-0F-4 DATA SELEC T O RS/M U LTIPLEXER S WITH 3-STATE OUTPUTS TI0121— D3109. JUNE 19B8— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11 3 53 . . . J PACKA GE 7 4 A C T 11 3 53 . . . D OR N P ACKA G E • Inverting Versions of 54ACT11253 and

MB7132E

Abstract: b7131 mb7132 LSK Series MB7132Y
Contextual Info: FUJITSU PROGRAMMABLE SCHOTTKY 8192-BIT READ ONLY MEMORY M B7131E/H/L M B7132E/H/Y/L MB7131E-SK/H-SK/L-SK M B7132E-SK/H -SK/Y-SK/L-SK I January 19B8 E d itio n 2.0 SCHOTTKY 8192-BIT DEAP PROM 1024 WORDS X 8 BITS The Fujitsu MB 7131 and MB 7132 are high speed sch ottky T T L electrically

LP311

Contextual Info: LP111, LP211, LP311 lu W-POWER DIFFERENTIAL COMPARATORS WITH STROBES ^ _ SLCS003A- JUNE 1987 - REVISED MAY 19B8 • Low Power Drain . . . 900 iW Typical With 5-V Supply • Operates From ±15 V or From a Single Supply as Low as 3 V

TMS27C210

Contextual Info: TMS27C210 1,048,576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY MAY 1 98 7 —REVISED JUNE 19B8 W ide-W ord Organization . . . 64K x 16 J PACKAGE TOP VIEW 1 LAo É C Q 16 Q 2 39 40-Pin Dual-In-line Package 3 38 £ 4 37 □ A15 Q 14 Q 5 36 6 35 £ £ 7

Contextual Info: SN5474, SN54LS74A, SN54S74, SN7474, SN74LS74A, SN74S74 DUAL D TYPE POSITIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D E C E M B E R 1983 - R E V IS E D M A R C H 19B8 Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers

Contextual Info: SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J K FLIP FLOPS WITH CLEAR DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Sm all O utline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs S N 5 4 1 0 7 , S N 5 4 L S 1 0 7 A . . . J PACKAGE

TE 2161

Abstract: TE 2162 7b1l
Contextual Info: TL750L, TL751L SERIES LOW-DROPOUT VOLTAGE REGULATORS D3017. SEPTEMBER I987~REVISED FEBRUARY 19B8 • Very Low Dropout Voltage, Less than 0 .6 V at 150 mA • Very Low Quiescent Current • TTL- and CMOS-Compatible Enable On TL751L Series • 60-V Load-Dump Protection

PZK 20

Abstract: 5.5v 1.0f 74AC11253 pht 094 54AC11253 D3108
Contextual Info: 54AC11253, 74AC11253 DUAL 1-0F-4 DATA SELECTORS/DEMULTIPLEXERS WITH 3-STATE OUTPUTS TI0136— D3108, MAY 19B8— REVISED MARCH 1990 54AC11253 . . . J PACKAGE 74AC11253 . . . D O R N PACKAGE Permits Multiplexing from N Lines to 1 Line Performs Parallel-to-Serial Conversion

MB47201

Abstract: mb472 Q20J
Contextual Info: F U J IT S U QUAD SPST BI-FET ANALOG SWITCH MB47201 M ay 19B8 E dition 1.0 QUAD SPST BI-FET ANALOG SWITCH The F ujitsu MB47201 is a quad SPST S in gle-pole S ignal-T hro w B I-F E T analog sw itch m a n u fa c tu re d using Fujitsu A d vanced Bipolar Tech nolo gy. The

SCAD002

Abstract: SN74ACT2150A D416D
Contextual Info: 521 x SN74ACT2150A 8 CACHE ADDRESS COMPARATOR D3183, NO VEM BER 19B8— REVISED MARCH 1990 DW, JD, OR NT PACKAGE TOP VIEW Address to MATCH Valid Time - ACT2150A 20 ns MAX - ’ACT2150A 30 ns MAX RESET[ 1 300-Mil 24-Pin Ceramic Side-Brazed or Plastic Dual-ln-Line or Small Outline

Contextual Info: TL714C HIGH-SPEED DIFFERENTIAL COMPARATOR SLCSQ15 - DECEMBER 19B8 - REVISED JUNE 1989 Operates From a 5-V Supply Self-Biasing Inputs Hysteresis . . . 10 mV Typ Response Time. . . 6 ns Typ Maximum Operating Frequency 50 MHz Typ D OR P PACKAGE TOP VIEW NC

Contextual Info: SN54LS540, SN54LS541, SN74LS540, SN74LS541 OCTAL BUFFERS ANO LINE DRIVERS WITH 3 STATE OUTPUTS D2546, AUGUST 1979-REVISED MARCH 19B8 • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers S N 5 4 L S 5 4 0 . S N 5 4 L S 5 4 1 . . . J OR W P AC K A G E

TE3300

Contextual Info: SN65C1154, SN75C1154 QUADRUPLE LOW POWER DRIVERS/RECEIVERS D 3 2 3 0 , DECEMBER 19B8 D W OR N P AC KAG E M e e ts S ta n d a rd E IA -2 3 2 -D Revision of R S -2 3 2 C • V e ry L o w P o w er C onsum ption . . . 5 m W Typ • W id e D river S upply V o lta g e . . .

Contextual Info: LT1013, LT1013A, LT1013D, LT1013Y DUAL PRECISION OPERATIONAL AMPLIFIERS S L Q S 0 1 8 B -M A Y 19B8 - R EVISED OCTO BER 1996 Single-Supply Operation: Input Voltage Range Extends to Ground Output Swings to Ground While Sinking Current D PACKAGE TOP VIEW Input Offset Voltage

Contextual Info: TEXAS INSTR {LOGIC} OLE D | a ^ i 7 2 3 DD7ai2T □ | SN54F280B, SN74F280B 9-BIT PARITY GENERATORS/CHECKERS T 'V ^ / 7 D2932, APRIL 1 9 8 6 -R E V IS E D M A RC H 19B8 • Generates Either Odd or Even Parity for Nine Date Lines • Cascadable for n-Bits Parity

k55c12

Abstract: TL O74 SN54121 SN74121 74 family 73265
Contextual Info: SN54121, SN74121 MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SDLS042 M AY 1983 - REVISED MARCH 19B8 S N 5 4 1 2 1 . . . J OR W PAC KAG E Programmable O utput Pulse Width With Rj n t . . . 35 ns Typ With Rext/C ext . . . 40 ns to 28 Seconds SN 74121 , , . NPACKAG E