1992 Search Results

Contextual Info: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPSQ12A - D3523, JUNE 1 9 9 0 -R E V IS E D MARCH 1992 JT P A C K A G E Second-Generation PLD Architecture TO P V IE W High-Performance Operation: fmax (External Feedback). . . 33.3 MHz

Contextual Info: SN75LBC241 LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS SLLS137E - MAY 1992 - REVISED JANUARY 1999 • Operates With Single 5-V Power Supply • Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 • Improved Performance Replacement for

ST NE556

Abstract: NES56 NE556J NE556 applications NE555
Contextual Info: NES56, SA556, SE556, SE556C DUAL PRECISION TIMERS SLFS023A - A P R IL 1978 - REVISED O CTO BER 1992 • Two Precision Timing Circuits per Package • Astable or Monostable Operation • TTL-Compatible Output Can Sink or Source Up to 150mA • Active Pullup or Pulldown

1d4 cb

Contextual Info: SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS S CB S160 - DE CE M B E R 1992 Members of the Texas Instruments Widebus Family SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE TOP VIEW State-of-the-Art EPIC-llB™ BiCMOS Design

Contextual Info: SN74ALS233B 16x5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253 - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs DW OR N PACKAGE TOP VIEW • 16 Words by 5 Bits OE [ 1 FULL-1 [ 2 • Data Rates From 0 to 40 MHz • Fall-Through Ti me. . . 14 ns Typ

Contextual Info: SCDS002C - NOVEMBER 1992 - REVISED MAY 1995 DB, DW, OR PW PACKAGE TOP VIEW Functionally Equivalent to QS3245 Standard '245-Type Pinout 5-iî Switch Connection Between Two Ports NC [ 1 A1 [ 2 TTL-Compatible Control Input Levels A2 [ 3 A3 [ 4 A4 [ 5 Package Options Include Shrink

LM311 application notes

Abstract: LM311 LM3111 LM311 OPERATIONAL AMPLIFIER OPERATION lm311 application note LM311 application SLCS007A LM311DBLE 100 khz crystal
Contextual Info: LM111, LM211, LM311, LM311Y DIFFERENTIAL COMPARATORS WITH STROBES SLCS007A- SEPTEMBER 1973 - REVISED FEBRUARY 1992 Fast Response Times LM111 . . . J PACKAGE TOP VIEW Strobe Capability Maximum Input Bias C u rren t. . . 300 nA NC[ 1 EMIT O U T [ 2 Maximum Input Offset C u rren t. . . 70 nA

Contextual Info: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted

Contextual Info: SN74ALS229B 16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SPAS09Q - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits • Data Rates From 0 to 40 MHz • Fall-Through Time. . . 14 ns "typ • 3-State Outputs

26c32c

Abstract: 26C32I
Contextual Info: AM26C32C, AM26C32I QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS104B- D3634, DECEMBER 1990-R EV ISE D DECEMBER 1992 Meets EIA Standards RS-422-A, RS-423-A, and CCITT Recommendation V.11 □, N, OR N S t PACKAGE TOP VIEW Low Power, Ice = 9 rnA Typ 1B[ ±7-V Common-Mode Range With ±200-mV

Contextual Info: TMS28F040 4 194 304-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SMJS040-DECEMBER 1992 N PACKAGET Organization . . . 512K x 8 Separately Erasable 32K Byte Blocks Two Power Supplies 5 V and 12 V 100% TTL-Level Control Inputs Fully Automated On-Chip Erase and Byte

44460D

Abstract: BK36C-80
Contextual Info: TM124MBK36C, TM124MBK36S1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS138B - MARCH 1992 - REVISED JUNE 199S Enhanced Page Mode Operation With CAS-Before-RAS CBR , RAS-Only, and Hidden Refresh Presence Detect Performance Ranges:

LM311

Abstract: ic lm311 circuit diagram LM311 application notes SLCS007A LM311DBLE LM311T LM111 fk package
Contextual Info: LM111, LM211, LM311, LM311Y DIFFERENTIAL COMPARATORS WITH STROBES SLCS007A-SEPTEMBER 1 9 7 3 - REVISED FEBRUARY 1992 LM111 . . . J PACKAGE Fast Response Times TOP VIEW Strobe Capability Maximum Input Bias C u rre n t. . . 300 nA NC[ EMIT O U T [ IN + [ IN -[

d3798

Abstract: ABT16543
Contextual Info: SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087A - D379B, FEBRUARY 1991 - R EVISED O CTO BER 1992 Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-llB™ BiCMOS Design Significantly Reduces Power Dissipation

27LV010A

Contextual Info: TMS27LV010A1 048 576-BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM TMS27LV010A1 048 576-BIT LOW VOLTAGE ONE-TIME PROGRAMMABLE ROM SMLS113-DECEMBER 1992 x 8 J AND N PACKAGESt TOP VIEW Single 3.3-V Power Supply Operationally Compatible With Existing 1-Megabit EPROMs

ua741c

Abstract: IC uA741 UA7411 OF IC UA741 fairchild A741 UA741MFK uA741MU ua741c texas
Contextual Info: UA741C, UA741I, UA741M GENERAL-PURPOSE OPERATIONAL AMPLIFIERS _ D920, NOVEMBER 1970 — REVISED JANUARY 1992 Short-Circuit Protection U A 741M . . . J PACKAGE TOP VIEW Offset-Voitage Null Capability NC[ 1 NC[ 2 Large Common-Mode and Differential

TLC371MD

Contextual Info: TLC371, TLC371Y LinCMOS DIFFERENTIAL COMPARATORS ^ _SLCSQ17 - JULY 1991 - R EVISED FEBRUARY 1992 • Single or Dual-Supply Operation D OR P PACKAGE TOP VIEW • Wide Range of Supply Voltages 3 V to 16 V IN - [ 2 a ] V DD

Contextual Info: SN54LVT240A, SN74LVT240A 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134H - SEPTEMBER 1992 - REVISED AUGUST 1997 State-of-the-Art Advanced BiCMOS Technology ABT Design for 3.3-V Operation and Low Static Power Dissipation SN54LVT240A . . . J PACKAGE

Contextual Info: CDC392 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS _ SCAS335A-DECEMBER 1992-R E V IS E D NOVEMBER 1995 D PACKAGE TOP VIEW Low Output Skew for Clock-Distribution and Clock-Generatlon Applications

Ks-7b

Contextual Info: TMS417800, TMS417800P 2 097152 WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORIES S M K S 7 8 0 -D E C E M B E R 1992 x 8 DE P AC K A G E t DZ P A C K AG E t TOP VIEW (TOP VIEW) * Performance Ranges: vcc[ 1o D Q 0[ 2 ACCESS ACCESS ACCESS READ TIME TIME TIME OR WRITE

27c040-12

Contextual Info: SMJ27C040 524288 BY 8-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SGMS046B - NOVEMBER 1992 - REVISED SEPTEMBER 1997 Organization . . . 524288 by 8 Bits Single 5-V Power Supply Industry Standard 32-Pin Dual-In-line Package All Inputs/Outputs Fully TTL Compatible

d2901

Abstract: tlc274cn
Contextual Info: TLC354, TLC354Y LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116- D2901, SEPTEMBER 1985 - REVISED DECEMBER 1992 • • • • • • • • • • • Single- or Dual-Supply Operation

44-800-p

Abstract: 44800P PIN DIAGRAM of IC AD 524 IN2045
Contextual Info: TMS44800, TMS44800P 524 288-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMHS480B-1992-REVISED DECEMBER 1992 This data sheet is applicable to all TMS44800/Ps symbolized with Revision“B" and subsequent revisions as described on page 22. * Organization . . . 524 288 x 8

SPW 12w

Abstract: TMS380c16 RRU 32
Contextual Info: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options