18-LEAD D-6 PACKAGE Search Results

CDIP2-T18

Abstract: 2N18 18-LEAD D-6 PACKAGE
Contextual Info: Hermetic Packages for Integrated Circuits Ceramic Dual-In-Line Metal Seal Packages SBDIP D18.3 MIL-STD-1835 CDIP2-T18 (D-6, CONFIGURATION C) LEAD FINISH c1 -A- 18 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE -DBASE METAL E b1 M (b) M -Bbbb S C A - B S SECTION A-A

27BSC

Abstract: marking 62m
Contextual Info: WTK9410 8 D S 7 D S 2 P b Lead Pb -Free 1 Surface Mount N-Channel Enhancement Mode MOSFET 6 D 3 S DRAIN CURRENT 18 AMPERES DRAIN SOURCE VOLTAGE 30 VOLTAGE 5 D 4 G Features: * Simple Drive Requirement. * Low On-Resistance. * Fast Switching. * Super high dense cell design for low RDS(ON)

MS 21340-05

Abstract: MS24331 JCA 812 MIL-W-5088 MIL-S-8805 MS2508I-C6
Contextual Info: MICRO SWITCH r FREEPORT, IL L IN O IS . A D IV IS IO N OF M FG . 4 E N 1 -6 SWITCH-ENCLOSED U S A HONEYW ELL MILITARY STDS PART NO. MS 243 31 - 4 CODE 9 1 9 2 9 St FED. C A T A L O G L IS T IN G lf> 1.50 DIA 8 NO. 18 WIRE LEAD PER M IL - W - 2 2 7 5 9 / 7 MARKED WITH

IRFBC30

Abstract: IRFBC20 IRFBC40 IRFPE50 IRS2106 IRS21064
Contextual Info: Data Sheet No. PD60246 IRS2106/IRS21064 S PbF HIGH AND LOW SIDE DRIVER Features Packages • Floating channel designed for bootstrap operation • Fully operational to +600 V • Tolerant to negative transient voltage, dV/dt immune 8-Lead PDIP • Gate drive supply range from 10 V to 20 V

DD 127 D TRANSISTOR

Abstract: FK 231 SA 220 transistor fn 1016 LTC DWG FN 1016 dp 502 t TO 220 MOT E SO18 TI 3-Lead Plastic DD Pak ltc m 5-Lead Plastic DD Pak ltc Q
Contextual Info: PACKAGE PACKAGE CROSSDIMENSIONS REFERENCE LCC METAL CAN CERDIP Ceramic Dual-In-Line METAL CANS SSOP Shrink Small Outline TSSOP Thin Shrink Small Outline SIDE BRAZED PACKAGE OUTLINE DESCRIPTION LTC NSC MOT TI LINFIN MAXIM 8-Lead Side Brazed Hermetic D8 D

Contextual Info: SPEC NO. 05-08-5014 REV. U REV A B C D E F G H J RH1014M, QUAD PRECISION OPERATIONAL AMPLIFIER REVISION RECORD DESCRIPTION INITIAL RELEASE • PAGE 2, ADDED PARAGRAPHS 3.2.1 AND 3.2.2 TO IDENTIFY “01” AND “02” AS PACKAGE OPTIONS. CHANGED THE PART NUMBER FROM”RH1014MWB14 TO “RH1014MWB”.

Contextual Info: lozu profite t 2l COMPATIBLE 10-TAP tO G IC DELAY MODULE # T2L input and outputs # Delays stable and precise # 14-pin DIP package time is measured at the +1.5V level on the leading edge. Rise time for all modules is 4ns maximum when measured from 0.8V to 2.0V. Temperature coefficient of delay is approxi­

ASEA

Abstract: MS-013-AB MS-012-AC MS 013AA MS-013-AA MA007 MS-012AB Package
Contextual Info: PACKAGE OUTLINES PLASTIC SOIC 0.150” body width PACKAGE DESIGNATOR L Dimensions in Inches (for reference only) N 0.0098 0.0075 0.1574 0.1497 0.020 0.013 0.2440 0.2284 1 2 0.050 3 BSC D 0.050 0.016 0° TO 8° 0.0688 0.0532 0.0040 MIN. N Number of Leads

LTC DWG 05-08-1661

Abstract: ks 15544 transistor FN 1016 MS10 SO18 SO20 SO24 WO10 TO253 WO14
Contextual Info: PACKAGE PACKAGE CROSSDIMENSIONS REFERENCE SIDE BRAZED PACKAGE OUTLINE DESCRIPTION LTC NSC MOT TI LINFIN MAXIM 8-Lead Side Brazed Hermetic D8 D D ADI/PMI — l — — DA 14-, 16-, 18- and 20-Lead Side Brazed (Hermetic) D D D YB QB XB L — — DD, DE, DN, DP

rs-24v

Abstract: rs 24v
Contextual Info: SCOPE: CMOS, TTL-COMPATIBLE ANALOG MULTIPLEXER Device Type 01 02 Generic Number DG528A x /883B DG529A(x)/883B Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows: Outline Letter K Z Case Outline Package Code Mil-Std-1835 GDIP1-T18 or CDIP2-T18

14.5M 1982

Abstract: AC12 MO-220 MO-275 ANSI Y14.5 FCBGA304 fcbga-304 ansi-y14.5m-1982 LAttice bottom marking SCM40
Contextual Info: Package Diagrams November 2010 Data Sheet 20-Pin 300-Mil CERDIP Package Dimensions in Inches (DATUM A) B 1 N/2 4 E E1 N E3 e/2 E DETAIL A D A 4 BASE PLANE (DATUM B) A2 A1 A C SEATING PLANE e b2 Z b .010 M L E2 C A B b1 (c) 4X WITH LEAD FINISH c1 BASE METAL

7361

Abstract: TPME228 E5565
Contextual Info: TPM Multianode Tantalum Ultra Low ESR Capacitor Low ESR, high capacitance and high ripple current are the key parameters for processor filtering. Multianode configuration within a standard E case package meets these requirements. Parameters such as ESR 15mΩ, capacitance 1500µF and ripple

SN74ALS32P

Contextual Info: SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDAS113B – APRIL 1982 – REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

LT1460BCS3-10

Abstract: marking code LTGG LTGF marking code sot 23 MARK LTGG LTKD MARKING CODE ltbw LM 3937 LT1460BCS3-2 LT1521CS8-3 LTHS
Contextual Info: PACKAGE PACKAGE CROSSDIMENSIONS REFERENCE LCC METAL CAN CERDIP Ceramic Dual-In-Line METAL CANS SSOP Shrink Small Outline TSSOP Thin Shrink Small Outline SIDE BRAZED PACKAGE OUTLINE DESCRIPTION LTC NSC MOT TI LINFIN MAXIM 8-Lead Side Brazed Hermetic D8 D

117450

Abstract: TO253 lt941 ltc947 1624i LT 129i5 sm 2178a LT1510CGN sot23 1303 ltbw 83
Contextual Info: PACKAGE PACKAGE CROSSDIMENSIONS REFERENCE SIDE BRAZED PACKAGE OUTLINE DESCRIPTION LTC NSC MOT TI LINFIN MAXIM 8-Lead Side Brazed Hermetic D8 D D ADI/PMI — l — — DA 14-, 16-, 18- and 20-Lead Side Brazed (Hermetic) D D D YB QB XB L — — DD, DE, DN, DP

59628768901VA

Contextual Info: SCOPE: CMOS, TTL-COMPATIBLE ANALOG MULTIPLEXER Device Type 01 Generic Number DG528A x /883B Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows: Outline Letter K Mil-Std-1835 GDIP1-T18 or CDIP2-T18 Case Outline Package Code

Contextual Info: SQM18N33-160H www.vishay.com Vishay Siliconix Automotive N-Channel 330 V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY VDS (V) • TrenchFET Power MOSFET 330 RDS(on) () at VGS = 10 V • Package with Low Thermal Resistance 0.160 ID (A) • AEC-Q101 Qualified

Contextual Info: SN54ALS534A, SN74ALS534A, SN74AS534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS168B – APRIL 1982 – REVISED JULY 1996 SN54ALS534A . . . J PACKAGE SN74ALS534A, SN74AS534 . . . DW OR N PACKAGE TOP VIEW 3-State Bus Driving Inverting Outputs

HCS273KMSR

Abstract: HCS273 HCS273DMSR HCS273HMSR HCS273MS
Contextual Info: HCS273MS Radiation Hardened Octal D Flip-Flop September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

CA3261

Abstract: A3261 CA3202E as-001a ca3154e CA3157G ca3202
Contextual Info: ••■«•i*^¡" s*. R C il^ State CA3261 Linear Integrated Circuits Advance Information AFC/Horizontal Oscillator Signal Processor With Sync Separator and A G C Features: rn ; if 4' ! II i> ? : H -1 8 9 9 18-L*ad DuaMit-Une Plastic Package E Suffix ■

AUDIO CIRCUIT 6283

Contextual Info: TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. D D D Power-On Reset Generator Automatic Reset Generation After Voltage Drop RESET Output Defined From VCC ≥ 1 V Precision Voltage Sensor TL77xxBC . . . D OR P PACKAGE

Contextual Info: Hermetic Packages for Integrated Circuits Ceramic Metal Seal Flatpack Packages Flatpack K18.B A e 18 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A INCHES PIN NO. 1 ID AREA SYMBOL -A- D -B- S1 b MIN MILLIMETERS MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015

K18C

Contextual Info: Hermetic Packages for Integrated Circuits Ceramic Metal Seal Ceramic Lid Flatpack Packages Flatpack K18.C A e 18 LEAD CERAMIC METAL SEAL CERAMIC LID FLATPACK PACKAGE A PIN NO. 1 ID AREA INCHES -A- D -B- S1 b E1 0.004 M H A-B S Q D S 0.036 M H A-B S D S C

Contextual Info: SQM18N33-160H www.vishay.com Vishay Siliconix Automotive N-Channel 330 V D-S 175 °C MOSFET FEATURES PRODUCT SUMMARY VDS (V) • TrenchFET Power MOSFET 330 RDS(on) () at VGS = 10 V • Package with Low Thermal Resistance 0.160 ID (A) • AEC-Q101 Qualified