18 10A Search Results

sm 4205

Abstract: 64x18 synchronous sram
Contextual Info: CY7C4425/4205/4215 CY7C4225/4235/4245 PRELIMINARY 64, 256,512, 1K ,2K ,4K x 18 Synchronous FIFOs Features • • • • • • • • • • • • 64 x 18 CY7C4425 256 x 18 (CY7C4205) 512 x 18 ( CY7C4215) IK x 18 (CY7C4225) 2K x 18 (CY7C4235) 4K x 18 (CY7C4245)

4279g

Abstract: G52E111 G74B111 ET-46 microtran t5115 IFS-0505 TTC05 TTC 103 2PC 502 m 8044
Contextual Info: ~tamura Product Number Index MICROTRAIM, Part No. Page Part No. Page 1 0A 006 20 3FD -348 18 Part No. 3FS -2120 Page 18 630A4201 33 A K S 25-12 39 DCM 4-PC 10A 007 20 3FD -356 18 3FS -216 18 630 A 4 3 0 4 33 A K S 25-15 39 DCM 5-PC 6 1 0A 008 20 3FD -410 18

eljo trend uttag

Abstract: ELJO eljo trend IP44-montage
Contextual Info: EL JO TIMER Elektroniska timrar, 2-poliga IP20 och IP44 Elektronisk timer med vägguttag Utanpåliggande Elektronisk timer Infälld TEKNISK INFORMATION E-nummer: E 18 978 E 18 978 E 18 978 E 18 978 E 18 978 60 61 72 73 69 Eljo Eljo Eljo Eljo Eljo Trend Trend

C4425

Contextual Info: fax id: 5410 CY7C4425/4205/4215 CY7C4225/4235/4245 64, 256, 512, 1K , 2K, 4K x 18 Synchronous FIFOs F e a tu re s • High-speed, low-power, first-in first-out FIFO memories • 64 x 18 (CY7C4425) • 256 x 18 (CY7C4205) . 512 x 18 (CY7C4215) • 1 K x 18 (CY7C4225)

3M Touch Systems

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

SB100-18

Abstract: EN2580B
Contextual Info: SB100-18 Ordering number : EN2580B SANYO Semiconductors DATA SHEET SB100-18 Schottky Barrier Diode Twin Type • Cathode Common 180V, 10A Rectifier Applications • High frequency rectification (switching regulators, converters, choppers). Features • •

EN2580

Abstract: SB100-18
Contextual Info: SB100-18 Ordering number : EN2580B SANYO Semiconductors DATA SHEET SB100-18 Schottky Barrier Diode Twin Type • Cathode Common 180V, 10A Rectifier Applications • High frequency rectification (switching regulators, converters, choppers). Features • •

3M Touch Systems

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • 18-Mbit density (2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36)

3M Touch Systems

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • 18-Mbit density (2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36)

Contextual Info: 5TCYPRESS PRELIMINARY 64,256,512, IK, 2K, 4 K x l8 Synchronous FIFOs Features • Output Enable OE pin • • • • • • • • 68-pin PLCC and 64-pin TQFP • • • • • 64 x 18 (CY7C4425) 256 x 18 (CY7C4205) 512 x 18 ( CY7C4215) IK x 18 (CY7C4225)

3M Touch Systems

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency) Features Functional Description • 18-Mbit density (2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36)

Contextual Info: LTC2389-18 18-Bit, 2.5Msps SAR ADC with Pin-Configurable Analog Input Range and 99.8dB SNR DESCRIPTION FEATURES n n n n n n n n n n n n n n n The LTC 2389-18 is a low noise, high speed 18-bit successive approximation register SAR ADC. Operating from a single 5V supply, the LTC2389-18 supports pinconfigurable fully differential (±4.096V), pseudo-differential unipolar (0V to 4.096V), and pseudo-differential

CY7C1392V18

Abstract: CY7C1393V18 CY7C1394V18
Contextual Info: 392V18 CY7C1392V18 CY7C1393V18 CY7C1394V18 ADVANCE INFORMATION 18-Mb SRAM with DDR-II SIO Architecture Features Functional Description • 18-Mb Density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth

EN2580

Abstract: SB100-18 25802 EN2580A
Contextual Info: Ordering number :EN2580A SB100-18 Schottky Barrier Diode Twin Type • Cathode Common 180V, 10A Rectifier Applications Package Dimensions · High frequency rectification (switching regulators, converters, choppers). unit:mm 1160 [SB100-18] Features · Low forward voltage (VF max=0.85V).

Contextual Info: W CYPRESS PRELIMINARY 64, 256, 512, IK, 2K, 4K x 18 Synchronous FIFOs Features • O utput E n ab le Ü Ê pin • 64 x 18 (CY7C4425) • 68-p in P L C C a n d 6 4 -p in T Q F P • 256 x 18 (CY7C4205) Functional D escription • 512 x 18 ( CY7C4215) •

Contextual Info: • Standard Quarter Brick Footprint • 18-36VDC, 36-75VDC & Wide Range 18-60V Inputs • 3.3V 40A - 15V 10A Nominal Outputs • Through Hole Mounting Key Market Segments & Applications • Low 10.41mm Key Market Profile Segments & Applications Test & Measurement

IQE24007A15

Abstract: IQE24007A150V-001-R IQE24007A150V-007-R IQE24009A120V-007-R iqe4w011a120v-001-r VDE0805
Contextual Info: • Standard Quarter Brick Footprint • 18-36VDC, 36-75VDC & Wide Range 18-60V Inputs • 3.3V 40A - 15V 10A Nominal Outputs • Through Hole Mounting Key Market Segments & Applications • Low 10.41mm Key Market Profile Segments & Applications Test & Measurement

iqe4w011a120v-001-r

Abstract: IQE24007A150V-001-R IQE24007A150V-007-R VDE0805
Contextual Info: • Standard Quarter Brick Footprint • 18-36VDC, 36-75VDC & Wide Range 18-60V Inputs • 3.3V 40A - 15V 10A Nominal Outputs • Through Hole Mounting Key Market Profile Segments & Applications • Low 10.41mm Key Market Segments & Applications Test & Measurement

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth

CY7C1317V18

Abstract: CY7C1319V18 CY7C1321V18
Contextual Info: CY7C1317V18 CY7C1319V18 CY7C1321V18 ADVANCE INFORMATION 18-Mb 4-Word Burst SRAM with DDR-II Architecture Features Functional Description • 18-Mb Density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth

CY7C11681KV18

Abstract: 3M Touch Systems
Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth