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Nexperia BZT52-B75X Zener Diodes ZENER SOD-123 .59W 75V
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
TTI	BZT52-B75X	Reel	39,000		3,000	1 - 10 - 100 - 1000 - 10000 $0.02	Buy Now
Bourns Inc 70F502AF-RC RF Inductors - Leaded 50mH 5%
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
TTI	70F502AF-RC	Bulk	15,000		2	1 - 10 $4.43 100 $4.43 1000 $3.13 10000 $2.98	Buy Now
Eaton Corporation DRA127-101-R Power Inductors - SMD 100uH 3.46A 0.175ohms
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
TTI	DRA127-101-R	Reel	7,000		350	1 - 10 - 100 - 1000 $1.24 10000 $0.79	Buy Now
Vishay Intertechnologies ZM4761A-GS08 Zener Diodes 75 Volt 1 Watt 5%
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
TTI	ZM4761A-GS08	Reel	3,000		1,500	1 - 10 - 100 - 1000 - 10000 $0.11	Buy Now
Vishay Intertechnologies PCAN1206E1750BST5 Thin Film Resistors - SMD 2 Watt 175ohm 25ppm 0.1% 1206 SMD
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
TTI	PCAN1206E1750BST5	Reel	2,000		500	1 - 10 - 100 - 1000 $0.93 10000 $0.88	Buy Now

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175OHMS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY7C1305V25-167BZC Abstract: CY7C1305V25 CY7C1307V25 Contextual Info: 1305V25 CY7C1305V25 CY7C1307V25 Preliminary 18 Mb Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time	Original	1305V25 CY7C1305V25 CY7C1307V25 CY7C1305V25-167BZC CY7C1305V25 CY7C1307V25	PDF
Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency	Original	CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb 250-MHz Page10)	PDF
Contextual Info: yy CY7C1302BV25 Preliminary 9 Mb Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1302BV25 CY7C1302BV25 38-05XXX	PDF
CY7C1311AV18 Abstract: CY7C1313AV18 CY7C1315AV18 Contextual Info: CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency	Original	CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb 250-MHz CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 CY7C1311AV18 CY7C1313AV18 CY7C1315AV18	PDF
CY7C1515V18 Abstract: CY7C1526V18 CY7C1511V18 CY7C1513V18 CY7C1515AV18 Contextual Info: CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 PRELIMINARY 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth	Original	CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit 250-MHz CY7C1515V18 CY7C1526V18 CY7C1511V18 CY7C1513V18 CY7C1515AV18	PDF
CY7C1515V18 Abstract: CY7C1511V18 CY7C1513V18 CY7C1515AV18 CY7C1526V18 Contextual Info: CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 PRELIMINARY 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth	Original	CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit 250-MHz CY7C1515V18 CY7C1511V18 CY7C1513V18 CY7C1515AV18 CY7C1526V18	PDF
CY7C1311AV18 Abstract: CY7C1313AV18 CY7C1315AV18 Contextual Info: CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency	Original	CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb 250-MHz CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 CY7C1311AV18 CY7C1313AV18 CY7C1315AV18	PDF
1034P Abstract: CY7C1303V25 CY7C1306V25 Contextual Info: yy yy yy CY7C1303V25 CY7C1306V25 Preliminary 18 Mb Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth	Original	CY7C1303V25 CY7C1306V25 1034P CY7C1303V25 CY7C1306V25	PDF