165 BALL Search Results

Contextual Info: THS4041, THS4042 165ĆMHz CĆSTABLE HIGHĆSPEED AMPLIFIERS ąą SLOS237B− MAY 1999 − REVISED FEBRUARY 2000 D C-Stable Amplifiers Drive Any Capacitive D D D D D D D THS4041 D AND DGN PACKAGE TOP VIEW Load High Speed − 165 MHz Bandwidth (−3 dB); CL = 0 pF

MT54W1MH18B

Abstract: MT54W2MH8B MT54W512H36B G38-87
Contextual Info: 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, QDRIIb2 SRAM 18Mb QDR II SRAM 2-WORD BURST MT54W2MH8B MT54W1MH18B MT54W512H36B Features Figure 1: 165-Ball FBGA • DLL circuitry for accurate output data placement • Separate independent read and write data ports with

Contextual Info: THS4041ĆQ1 165ĆMHz CĆSTABLE HIGHĆSPEED AMPLIFIER ą SGLS229A − FEBRUARY 2004 − REVISED APRIL 2004 D Qualification in Accordance With THS4041 D PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control

Contextual Info: TRF2443 www.ti.com SLWS217B – SEPTEMBER 2009 – REVISED MARCH 2012 Integrated IF Transceiver for Broadband Wireless Applications Check for Samples: TRF2443 FEATURES 1 • • • • • Integrated TX Chain 165–175 MHz / 330–350 MHz – Baseband Amplifiers

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb4 SRAM 36Mb QDR SRAM 4-WORD BURST MT54V2MH18E MT54V1MH36E Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE

Contextual Info: ADVANCE‡ 4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb4 SRAM 36Mb QDR II SRAM 4-WORD BURST MT54W4MH8J MT54W4MH9J MT54W2MH18J MT54W1MH36J FEATURES Figure 1 165-Ball FBGA • DLL circuitry for accurate output data placement • Separate independent read and write data ports with

Contextual Info: TFP403 TI PanelBus DIGITAL RECEIVER SLDS125A − DECEMBER 2000 − REVISED OCTOBER 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI 1.0) Specification Compliant1

Theta-JC

Contextual Info: TFP401, TFP401A TI PanelBus DIGITAL RECEIVER SLDS120B - MARCH 2000 − REVISED JUNE 2003 D Supports UXGA Resolution D D D D D D Reduced Power Consumption − 1.8 V Core Output Pixel Rates Up to 165 MHz Digital Visual Interface (DVI) Specification Compliant1

THS4041

Abstract: THS4041IDRQ1 10Log1
Contextual Info: THS4041ĆQ1 165ĆMHz CĆSTABLE HIGHĆSPEED AMPLIFIER ą SGLS229B − FEBRUARY 2004 − REVISED JUNE 2008 D Qualified for Automotive Applications D C-Stable Amplifier Drives Any Capacitive THS4041 D PACKAGE TOP VIEW Load NULL IN − IN + VCC− D High Speed

Contextual Info: TFP410 TI PanelBus DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 D Digital Visual Interface DVI Compliant1 D Supports Pixel Rates Up to 165 MHz D Enhanced Jitter Performance D Universal Graphics Controller Interface D D (Including 1080p and WUXGA at 60Hz)

Contextual Info: TLV5580 8ĆBIT, 80 MSPS LOWĆPOWER A/D CONVERTER www.ti.com SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 D 8-Bit Resolution 80 MSPS Sampling DW OR PW PACKAGE TOP VIEW Analog-to-Digital Converter (ADC) D Low Power Consumption: 165 mW Typ Using External references

Contextual Info: TFP501 PanelBus HDCP DIGITAL RECEIVER SLDS127B – JULY 2001 – REVISED AUGUST 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection

Contextual Info: TFP501 PanelBus HDCP DIGITAL RECEIVER SLDS127B − JULY 2001 − REVISED AUGUST 2002 D Supports UXGA Resolution Output Pixel D D D D D D 4x Over-Sampling for Reduced Bit-Error Rates up to 165 MHz Digital Visual Interface (DVI) and High-Bandwidth Digital Content Protection

Contextual Info: ADVANCE 256K x 36 2.5V VDD, HSTL, PIPELINED DDR SRAM 9Mb DDR SRAM MT57V256H36P FEATURES • • • • • • • • • • • • • • • • • • 165-Pin FBGA Fast cycle times: 3.3ns, 4ns, 5ns and 6ns 256K x 36 configuration Pipelined double data rate operation

Contextual Info: 307C.B.ABR Vishay Cera-Mite PTC Thermistors for Electronic Fluorescent Ballasts A MECHANICAL SPECIFICATIONS B Wire Coating Packaging RoHS Compliant C Copper Clad Steel, 100 % Sn Plated None Bulk Pack DIMENSIONS in millimeters Diameter A Thickness (B)

88-108 mhz w power

Abstract: 88-108 an power 88-108 mhz 55ht fm emitter 88-108 mhz Power w 88-108mhz fm transistor
Contextual Info: FM 150 150 Watts, 28 Volts Broadcast 88 - 108 MHz GENERAL DESCRIPTION The FM 150 is a high power COMMON EMITTER bipolar transistor. It is designed for FM systems in the frequency band 88-108 MHz. The device has gold thin-film metallization and diffused ballasting for proven highest MTTF.

FMB150

Abstract: an power 88-108 mhz ASI10588
Contextual Info: FMB150 NPN SILICON RF POWER TRANSISTOR DESCRIPTION: The ASI FMB150 is a high power transistor designed for FM broadcast system in 88-108 MHz range. It has diffused ballasting resistor to improve MTBF and high VSWR capability. PACKAGE STYLE .500 4L FLG .112x45°

SMD Transistor z6

Abstract: 37281 transistor 6 pin SMD Z2 transistor SMD Z2 motorola 986 MRF6408 z11 smd SMD 1206 RESISTOR 100 OHMS smd z5 transistor transistor amplifier 3 ghz 10 watts
Contextual Info: MOTOROLA Order this document by MRF6408/D SEMICONDUCTOR TECHNICAL DATA The RF Line MRF6408 NPN Silicon RF Power Transistor Designed for PCN and PCS base station applications, the MRF6408 incorporates high value emitter ballast resistors, gold metallizations and offers

SOP 8 200MIL

Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
Contextual Info: Renesas Memory General Catalog 2003.11 Renesas Memory General Catalog Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with

JEP95 MS-028

Contextual Info: SMM5146XZ 12.7 – 15.4GHz Down converter MMIC FEATURES • Wafer Level Chip Scale Package with Solder Ball • Integrated Balanced Mixer, LO Buffer Amplifier, Low Noise Amplifier and x2 multiplier • 10dB Conversion Gain :10dB • Input Third Order Intercept Point IIP3 : +2dBm

Contextual Info: IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: 200PIN DDR2 667 SO-DIMM 512MB With 32Mx16 CL5 TS64MSQ64V6M Description Placement The TS64MSQ64V6M is a 32M x 64bits DDR2-667 SO-DIMM. The TS64MSQ64V6M consists of 8pcs 32Mx16its DDR2 SDRAMs in 84 ball FBGA packages and a 2048 bits serial EEPROM on a 200-pin printed

Contextual Info: 200PIN DDR2 667 SO-DIMM 1GB With 64Mx8 CL5 JM667QSJ-1G Description Placement The JM667QSJ-1G is a 128M x 64bits DDR2-667 SO-DIMM. The JM667QSJ-1G consists of 16pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 200-pin printed

Contextual Info: 200PIN DDR2 800 SO-DIMM 512MB With 64Mx8 CL5 JM800QSJ-512M Description Placement The JM800QSJ-512M is a 64M x 64bits DDR2-800 SO-DIMM. The JM800QSJ-512M consists of 8pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 200-pin printed