160LEAD Search Results

0798d

Abstract: CF700 RSL-10
Contextual Info: LF3370 LF3370 DEVICES INCORPORATED High-Definition Video Format Converter High-Definition Video Format Converter DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 83 MHz Data Rate for HDTV Applications ❑ Supports Multiple Video Formats Bi-Directional Conversions:

interface 8254 with 8086

Abstract: C1996 DS1287 IEEE-1284 MC146818 NS486 NS486SXF 25-megabyte interfacing lcd with 8086 8086 interfacing with 8254 peripheral
Contextual Info: February 1997 NS486 TM SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems General Description The NS486SXF is a highly integrated embedded system controller incorporating an Intel486TM -class 32-bit processor all of the necessary System Service Elements and a

Reed-Solomon

Abstract: 32C9210 32C9810 32P4910
Contextual Info: SSI 32C9810 Ultra SCSI Interface Controller 260 Mbit/s, Headerless Support Prototype July 1997 The high level of integration within the SSI 32C9810 provides a major reduction in parts count when building an Ultra SCSI drive system. The SSI 32C9810 may be combined with the following components to create

Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os

Contextual Info: fax id: 6140 ^CYPRESS CY7C375Î UltraLogic 128-Macrocell Flash CPLD Features • • • • Functional Description 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

kt 84l

Contextual Info: CY7C385P CY7C386P » r CYPR ESS UltraLogic Very High Speed 4K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: Revision: Thursday, September 24,1992 MUR 23 1993 PRELIMINARY CYPRESS s7-W '" SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

pci to isa bridge

Abstract: dock connector docking connector pci isa 82380AB 82380PB PCI-to-ISA
Contextual Info: R Intel 380AB/PB Dock Set Product Overview 82380AB Mobile PCI-To-ISA Bridge MISA 82380PB Mobile PCI-To-PCI Bridge (MPCI) 290558-001 R Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

Contextual Info: HV582 Initial Release 96-Channel Data Driver With High Voltage Push-Pull Outputs General Description Features ► ► ► ► ► ► ► HVCMOS technology Operating output voltage of 90V Data clock speed 30MHz @ VDD = 5V Six data shift registers Data directional loading control

Contextual Info: HV582 96-Channel Data Driver With High Voltage Push-Pull Outputs Features HVCMOS technology Operating output voltage of 90V Data clock speed 30MHz @ VDD = 5V Six data shift registers Data directional loading control Outputs: enable, polarity, all high, all low

Contextual Info: PRELIMINARY Cr CY37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: fax id: 6146 s? CYPRESS Ultra37128 PRELIMINARY UltraLogic 128-Macrocell ISR™ CPLD • High speed Features — f MAX = 167 MHz • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — t PD = 6.5 ns — ts = 3.5 ns — JTAG compliant on board programming

Contextual Info: Xgjf PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

LF9502

Abstract: LMU217 ACCM 5 pin digital video mixer - tbc power supply 5 Volt LF3347 9027 scl110 LF3310 LF3311
Contextual Info: Company Profile LOGIC Devices Incorporated develops and markets high-performance integrated circuits that are utilized in a wide range of video and medical imaging processing, telecommunications, computing and military smart weapon applications. LOGIC Devices is commited to providing its customers with the highest performing

71V546

Contextual Info: 128K x 64 FLOW THROUGH ZBT SRAM 128K x 64 PIPELINE ZBT SRAM FEATURES: PRELIMINARY IDT7MBV4153SA IDT7MBV4154SA DESCRIPTION: • Low profile 160-lead AMP Free Height Surface Mount Board-toBoard Connector family 5mm-8mm plug options • High speed - 66 Mhz flow through, 100 Mhz pipeline

Contextual Info: L64105 MPEG-2 Audio/Video Decoder LOGIC Preliminary Datasheet The L64105 is an integrated, low-cost source audio/video A/V decoder for use in MPEG-2 A/V decoding systems. The system block diagram in Figure 1 shows an application of the L64105 within an MPEG-2 system.

4082

Abstract: c 4082 PBSRAM ci 4082
Contextual Info: PRELIMINARY IDT7MBV4150 IDT7MBV4151 IDT7MBV4152 128K x 64/256K x 72 SYNCHRONOUS PIPELINED BURST SRAM 256K x 72 BURST ZBT SRAM MODULE FAMILY FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and pipelined burst zero bus turnaround ZBT™ SRAM

Contextual Info: IBM14N1372 IBM14N3272 IBM14N6472 High Perform ance SRAM Modules Features • 256K, 512K, and 1MB secondary cache module family using Synchronous and Asynchronous SRAMs. • Organized as a 32K, 64K, or 128K x 72 package on a 4.3” x 1.1”, 160-lead, Dual Read-out DIMM

xcf5206

Abstract: xc68307 xc68040 XPC821 XC68HC901FN XC68EC060 lcd interface with 8051 MC68901 xc68lc060 motorola ZP fu
Contextual Info: Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

ADV7122JN80

Abstract: ADV7122KN80 AN8140K CXD2308Q
Contextual Info: - 292 - • fc'-r'tfftjlO £ s & ADV7122JN80, 50 ADV7122KN80, 50 AN8140K > - il U PC654 CXD2308Q ADV7150KS170/135/110/85 Analog Devices Analog D evices tö T S ? H V —- ANALOG DEVICES il - ® ® TFS TFS + 2 5 'C TFS 25"C TFS S ^ S E S I i ' - t- 80,5 OMSPS

4082

Abstract: D18 D16 family 128K x 64 SRAM tqfp IDT7MBV4150 c 4082
Contextual Info: Integrated Device Technology, Inc. PRELIMINARY IDT7MBV4150 IDT7MBV4151 IDT7MBV4152 128K x 64/256K x 72 SYNCHRONOUS PIPELINED BURST SRAM 256K x 72 BURST ZBT SRAM MODULE FAMILY FEATURES: DESCRIPTION: • Pin compatible module family for pipelined burst SRAM and

SCL SDA VSYNC HSYNC PXCK image

Abstract: KSV VCO SCHEMATIC mda VGA board Hsync Vsync VGA ypbpr to dvi AD9887 AD9887A AD9887AKS-100 AD9887AKS-140 AD9887AKS-170
Contextual Info: Dual Interface for Flat Panel Display AD9887A FEATURES APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TVs FUNCTIONAL BLOCK DIAGRAM ANALOG INTERFACE REF REFIN RAIN CLAMP CLAMP A/D

"XOR Gate"

Abstract: d-latch JK flip flop jk flip flop to d flip flop conversion atmel 160 pin Atmel CPLD In-System Program internal circuitry for sr flip flop R S Flip Flop Latch sr flip flop ATF1516AS-10QC160
Contextual Info: Features • High-density, High-performance, Electrically-erasable Complex • • • • • • • • • • Programmable Logic Device – 256 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 160, 192, 208-pins – 10 ns Maximum Pin-to-pin Delay