16-BIT INTEL MICROPROCESSOR ARCHITECTURE Search Results

HC- 543

Abstract: 7 segment LD 1106 BS 189 itt 6066P A80286 G3-G12 aos Lot Code Identification 231630 IC GE 6066 AI 723
Contextual Info: INTEL CORP -CUP/PRPHLS} in y fc.7E » • 4fl2t,17S 012tmfl ?T2 ■ l n t e l 386 TM DX MICROPROCESSOR 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers

Contextual Info: INTEL CORP -CUP/PRPHLS} b7E D • 402^175 OlEbMll in t ^ l Intel386 SX MICROPROCESSOR ■ Full 32-Bit Internal Architecture — 8-, 16-, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Runs ln t e l3 8 6 TM Software in a Cost Effective 16-Bit Hardware Environment

386SX CIRCUIT diagram

Abstract: i386SX
Contextual Info: A m 386 S X ^ Advanced Micro Devices High-Performance, 32-Bit Microprocessor with 16-Bit Data Bus DISTINCTIVE CHARACTERISTICS • Com patible with 386SX system s and software ■ 25- and 20-M Hz operating speeds ■ Pin-for-pin replacem ent of the Intel I386SX

Fortran-86

Abstract: EV80C186EC IC86 IC-86 intel asm-96 28F001BX-T 80C186 80C186EC 80C188EC C188
Contextual Info: EV80C186EC Evaluation Board Low Cost Code Evaluation Tool Intel’s EV80C186EC evaluation board provides a hardware environment for code execution and software debugging The board features the 80C186EC CHMOS 16-bit embedded microprocessor and all necessary memory and peripheral logic The 80C186EC

difference between intel 8086 and intel 80186 pro

Abstract: intel 80186 pin out 80186
Contextual Info: INTEL CORP in t@ UP/PRPHLS 31E D • 4fi5fql7S OCHlSTfc, 3 ■ T 7 - - V 9 - / 7- 80186 HIGH INTEGRATION 16-BIT MICROPROCESSOR ■ Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller

difference between intel 8086 and intel 80186 pro

Abstract: 44e 402
Contextual Info: INTEL CORP U P/ PR PH LS 44E D Bl 4fl2bl75 G104êG3 4 Q I T L 1 in1U. 80186 HIGH INTEGRATION 16-BIT MICROPROCESSOR • Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller

Intel i860

Contextual Info: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per

Contextual Info: 80960JS/JC 3.3 V Microprocessor Advance Information Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JS lx the Bus Clock

G1251

Abstract: GE NPX intel 8295 Block diagram microprocessor 8097 architecture i386 ex 80287 coprocessor architecture i387 d1251 M8087 M80B
Contextual Info: SÖE D HÔ2bl7S 012S1Û1 4Ô5 • ITL1 INTEL CORP U P / P R P H L S MILITARY ¡387 MATH COPROCESSOR ' T ' i\(\-\Z -Q 5 Full-Range Transcendental Operations for SINE, COSINE, TANGENT, ARCTANGENT and LOGARITHM High Performance 80-Bit Internal Architecture

FGT 313

Abstract: N06010 a3058c 271121 intel i860
Contextual Info: [ p fô iy iiM A O W in te L MILITARY i860 XR 32/64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Tw o Floating-Point Results per Clock High Perform ance Design

8251A programmable communication interface

Abstract: M8251A block diagram 8251A INTEL 8251A A8251 m8251
Contextual Info: a8251 Programmable Communications Interface June 1997, ver. 2 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ General Description a8251 MegaCore function that provides an interface between a microprocessor and a serial communication channel Optimized for FLEX® architecture

80960JA

Abstract: 80960JD 80960JT MCS 48
Contextual Info: 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet Product Features • ■ ■ ■ ■ Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS

Intel overdrive

Contextual Info: in t e i Intel486 SX M ICROPROCESSOR IM PORTANT— Read This Section Before Reading The Rest Of The Data Sheet This data sheet describes the Intel486 SX microprocessor, the Intel OverDrive™ Processor, and the l n t e l 4 8 7 TM S X Math Coprocessor. All normal text describes the functionality for the Intel486 SX microproces­

Contextual Info: in te * MILITARY i860 64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

AU-AIS

Abstract: SDH 209 E001 IXF6012 IXF6048 55236 GCIXF6012E w213 marking tuifdp marking f25 ku
Contextual Info: Intel IXF6012 51/155/622 Mbit/s SONET/SDH Cell/Packet Interface Datasheet Intel® IXF6012 is a single-chip interface solution for the transport of ATM cells or HDLC frames over SONET/SDH. Intel® IXF6012 can operate as a quad 51/155 Mbit/s or as a single

FGT 313

Contextual Info: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

Contextual Info: DATA SH EET JANUARY 1999 Revision 2.0 LXP730 Multi-Rate DSL Framer General Description The LXP730 is a multi-purpose Digital Subscriber Line DSL framer which complements the Level One SK70725/21 Enhanced MDSL Data Pump (EMDP) to provide seamless transport of data and voice signals over

ba 6414 fs

Abstract: RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP
Contextual Info: intei I860 XP MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction — Up to Two Floating-Point Results ■ High Performance Design — 40/50 MHz Clock Rate — 100 Peak Single Precision MFLOPS

IC GE 6066

Contextual Info: Intel386 SX MICROPROCESSOR • Full 32-Bit Internal Architecture — 8-, 16-, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Runs ln te l 3 8 6 TM Software in a Cost Effective 16-Bit Hardware Environment — Runs Same Applications and O.S.’s

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

132-Lead

Abstract: AD30/ako 451 960
Contextual Info: A E W Â N l ! DKIIF ß}[ü iflA 70® ß !0 in te l 80960J A /JF EMBEDDED 32-BIT MICROPROCESSOR High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers

Contextual Info: CUBIT-622 Device DATA SHEET PRODUCT PREVIEW DESCRIPTION FEATURES The CUBIT-622 device is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are built from a number of CUBIT-3,

8Khz Oscillator

Abstract: AFM2 PQFP160 ST10 STLC5465B 80C186 80C188
Contextual Info: STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

Contextual Info: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET DESCRIPTION FEATURES CUBIT®-Pro The CUBIT-3 is a single-chip VLSI solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are constructed from a number of CUBIT-3 devices, all